Messages in this thread | | | Subject | Re: [PATCH v2 07/10] phy: qcom-qmp: Add support for DP in USB3+DP combo phy | From | Jonathan Marek <> | Date | Thu, 3 Sep 2020 19:26:39 -0400 |
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On 9/2/20 7:02 PM, Stephen Boyd wrote:
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> +static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy) > +{ > + const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; > + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; > + u32 val, phy_vco_div, status; > + unsigned long pixel_freq; > + > + val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | > + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; > + > + /* > + if (lane_cnt == 4 || orientation == ORIENTATION_CC2) > + val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; > + if (lane_cnt == 4 || orientation == ORIENTATION_CC1) > + val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; > + */ > + /* > + * TODO: Assume orientation is CC1 for now and two lanes, need to > + * use type-c connector to understand orientation and lanes > + */ > + val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; > + > + writel(val, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); > + > + /* > + if (orientation == ORIENTATION_CC2) > + writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); > + else > + */ > + /* does this do anything? link_clock_sel_mux isn't set (bit 5) */ > + writel(0x5c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); > + > + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); > + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); > + > + switch (dp_opts->link_rate) { > + case 1620: > + phy_vco_div = 0x1; > + pixel_freq = 1620000000UL / 2; > + break; > + case 2700: > + phy_vco_div = 0x1; > + pixel_freq = 2700000000UL / 2; > + break; > + case 5400: > + phy_vco_div = 0x2; > + pixel_freq = 5400000000UL / 4; > + break; > + case 8100: > + phy_vco_div = 0x0; > + pixel_freq = 8100000000UL / 6; > + break; > + default: > + /* Other link rates aren't supported */ > + return -EINVAL; > + } > + writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); > + > + clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); > + clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); > + > + writel(0x04, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2); > + writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG); > + writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_CFG); > + writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG); > + writel(0x09, qphy->pcs + QSERDES_V3_DP_PHY_CFG); > + > + writel(0x20, qphy->serdes + QSERDES_COM_RESETSM_CNTRL);
Should be QSERDES_V3_COM_RESETSM_CNTRL and not QSERDES_COM_RESETSM_CNTRL, which is for older PHY versions.
> + > + if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, > + status, > + ((status & BIT(0)) > 0), > + 500, > + 10000)) > + return -ETIMEDOUT; > + > + writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG); > + > + if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, > + status, > + ((status & BIT(1)) > 0), > + 500, > + 10000)) > + return -ETIMEDOUT; > + > + writel(0x18, qphy->pcs + QSERDES_V3_DP_PHY_CFG); > + udelay(2000); > + writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG); > + > + return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, > + status, > + ((status & BIT(1)) > 0), > + 500, > + 10000); > +}
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