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SubjectRe: [PATCH 2/7] drm/msm/a5xx: Separate A5XX_PC_DBG_ECO_CNTL write from main branch
On Sat, Sep 26, 2020 at 02:51:41PM +0200, kholk11@gmail.com wrote:
> From: AngeloGioacchino Del Regno <kholk11@gmail.com>
>
> The "main" if branch where we program the other regsiters for the

Nit - regsiters -> registers

> Adreno 5xx family of GPUs should not contain the PC_DBG_ECO_CNTL
> register programming because this has logical similarity
> differences from all the others.
>
> A later commit will show the entire sense of this.

With that
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>

> Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> index 6262603e6e2e..f98f0844838c 100644
> --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> @@ -577,8 +577,6 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
> gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20);
> gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030);
> gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x20100D0A);
> - gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
> - (0x200 << 11 | 0x200 << 22));
> } else {
> gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40);
> if (adreno_is_a530(adreno_gpu))
> @@ -587,9 +585,14 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
> gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400);
> gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060);
> gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16);
> + }
> +
> + if (adreno_is_a510(adreno_gpu))
> + gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
> + (0x200 << 11 | 0x200 << 22));
> + else
> gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
> (0x400 << 11 | 0x300 << 22));
> - }
>
> if (adreno_gpu->info->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI)
> gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8));
> --
> 2.28.0
>

--
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a Linux Foundation Collaborative Project

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