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SubjectRe: [PATCH 5/7] drm/msm/a5xx: Fix VPC protect value in gpu_write()
On Sat, Sep 26, 2020 at 02:51:44PM +0200, kholk11@gmail.com wrote:
> From: Konrad Dybcio <konradybcio@gmail.com>
>
> The upstream API for some reason uses logbase2 instead of
> just passing the argument as-is, whereas downstream CAF
> kernel does the latter.
>
> Hence, a mistake has been made when porting:
> 4 is the value that's supposed to be passed, but
> log2(4) = 2. Changing the value to 16 (= 2^4) fixes
> the issue.

FWIW I think downstream is wrong. Its a lot more intuitive to pass the number of
registers that should be protected than to force a human to do math.

Jordan

> Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
> Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> index 00df5de3c8e3..b2670af638a3 100644
> --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> @@ -789,7 +789,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
>
> /* VPC */
> gpu_write(gpu, REG_A5XX_CP_PROTECT(14), ADRENO_PROTECT_RW(0xE68, 8));
> - gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 4));
> + gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 16));
>
> /* UCHE */
> gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16));
> --
> 2.28.0
>

--
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a Linux Foundation Collaborative Project

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