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Subject[PATCH v4 0/2] SM8150 and SM8250 dispcc drivers
Date
Add display clock drivers required to get DSI and DP displays working on
SM8150 and SM8250 SoCs.

Derived from downstream drivers. Notable changes compared to downstream:
- EDP clks removed (nothing uses these even in downstream it seems)
- freq_tbl values for dp_link clk is in Hz and not kHz

v2:
- updated dts example to reflect the change (first patch)
- updated config_ctl_hi1_val in sm8250 dispcc to latest downstream

v3:
- combined dt-binding: "gcc_disp_gpll0_clk_src" is needed by sc7180 too
- use the right order in drivers/clk/qcom/Kconfig

v4:
- Dropped combining yaml with sdm845/sc7180 dispcc
- Combined drivers into one (sm8250 driver + patched pll config for sm8150)
- Dropped uses of CLK_GET_RATE_NOCACHE (which was copied from downstream)
- Dropped CLK_SET_RATE_PARENT from some DP clocks (upstream phy design)

Jonathan Marek (2):
dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings
clk: qcom: Add display clock controller driver for SM8150 and SM8250

.../bindings/clock/qcom,dispcc-sm8x50.yaml | 93 ++
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/dispcc-sm8250.c | 1107 +++++++++++++++++
.../dt-bindings/clock/qcom,dispcc-sm8150.h | 1 +
.../dt-bindings/clock/qcom,dispcc-sm8250.h | 66 +
6 files changed, 1277 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
create mode 100644 drivers/clk/qcom/dispcc-sm8250.c
create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8150.h
create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8250.h

--
2.26.1

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