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SubjectRe: [PATCH 5/5] perf: arm_spe: Decode SVE events
Hi Andre,

On Tue, Sep 22, 2020 at 11:12:25AM +0100, Andre Przywara wrote:
> The Scalable Vector Extension (SVE) is an ARMv8 architecture extension
> that introduces very long vector operations (up to 2048 bits).
> The SPE profiling feature can tag SVE instructions with additional
> properties like predication or the effective vector length.
>
> Decode the new operation type bits in the SPE decoder to allow the perf
> tool to correctly report about SVE instructions.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../arm-spe-decoder/arm-spe-pkt-decoder.c | 48 ++++++++++++++++++-
> 1 file changed, 47 insertions(+), 1 deletion(-)
>
> diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
> index a033f34846a6..f0c369259554 100644
> --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
> +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
> @@ -372,8 +372,35 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf,
> }
> case ARM_SPE_OP_TYPE:
> switch (idx) {
> - case 0: return snprintf(buf, buf_len, "%s", payload & 0x1 ?
> + case 0: {
> + size_t blen = buf_len;
> +
> + if ((payload & 0x89) == 0x08) {
> + ret = snprintf(buf, buf_len, "SVE");
> + buf += ret;
> + blen -= ret;
> + if (payload & 0x2)
> + ret = snprintf(buf, buf_len, " FP");
> + else
> + ret = snprintf(buf, buf_len, " INT");
> + buf += ret;
> + blen -= ret;
> + if (payload & 0x4) {
> + ret = snprintf(buf, buf_len, " PRED");
> + buf += ret;
> + blen -= ret;
> + }
> + /* Bits [7..4] encode the vector length */
> + ret = snprintf(buf, buf_len, " EVLEN%d",
> + 32 << ((payload >> 4) & 0x7));
> + buf += ret;
> + blen -= ret;
> + return buf_len - blen;
> + }
> +
> + return snprintf(buf, buf_len, "%s", payload & 0x1 ?
> "COND-SELECT" : "INSN-OTHER");
> + }
> case 1: {
> size_t blen = buf_len;
>
> @@ -403,6 +430,25 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf,
> ret = snprintf(buf, buf_len, " NV-SYSREG");
> buf += ret;
> blen -= ret;
> + } else if ((payload & 0x0a) == 0x08) {
> + ret = snprintf(buf, buf_len, " SVE");
> + buf += ret;
> + blen -= ret;
> + if (payload & 0x4) {
> + ret = snprintf(buf, buf_len, " PRED");
> + buf += ret;
> + blen -= ret;
> + }
> + if (payload & 0x80) {
> + ret = snprintf(buf, buf_len, " SG");
> + buf += ret;
> + blen -= ret;
> + }
> + /* Bits [7..4] encode the vector length */
> + ret = snprintf(buf, buf_len, " EVLEN%d",
> + 32 << ((payload >> 4) & 0x7));
> + buf += ret;
> + blen -= ret;

The changes in this patch has been included in the patch [1].

So my summary for patches 02 ~ 05, except patch 04, other changes has
been included in the patch set "perf arm-spe: Refactor decoding &
dumping flow".

I'd like to add your patch 04 into the patch set "perf arm-spe:
Refactor decoding & dumping flow" and I will respin the patch set v2 on
the latest perf/core branch and send out to review.

For patch 01, you could continue to try to land it in the kernel.
(Maybe consolidate a bit with Wei?).

Do you think this is okay for you?

Thanks,
Leo

[1] https://lore.kernel.org/patchwork/patch/1288413/

> } else if (payload & 0x4) {
> ret = snprintf(buf, buf_len, " SIMD-FP");
> buf += ret;
> --
> 2.17.1
>

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