Messages in this thread | | | Subject | Re: [PATCH 11/12] soc: mediatek: pm-domains: Add support for mt8183 | From | Matthias Brugger <> | Date | Fri, 25 Sep 2020 11:07:35 +0200 |
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On 25/09/2020 10:21, Enric Balletbo i Serra wrote: > Hi Hsin-Yi and Matthias, > > Hsin-Yi, many thanks to provide the register names. > > On 25/9/20 9:37, Hsin-Yi Wang wrote: >> On Wed, Sep 16, 2020 at 8:19 PM Matthias Brugger <matthias.bgg@gmail.com> wrote: >>> >>> >>> >>> On 16/09/2020 11:46, Matthias Brugger wrote: >>>> >>>> >>>> On 10/09/2020 19:28, Enric Balletbo i Serra wrote: >>>>> From: Matthias Brugger <mbrugger@suse.com> >>>>> >>>>> Add the needed board data to support mt8183 SoC. >>>>> >>>>> Signed-off-by: Matthias Brugger <mbrugger@suse.com> >>>>> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> >>>>> --- >>>>> >>>>> drivers/soc/mediatek/mtk-pm-domains.c | 162 ++++++++++++++++++++++++++ >>>>> include/linux/soc/mediatek/infracfg.h | 28 +++++ >>>>> 2 files changed, 190 insertions(+) >>>>> >>>>> diff --git a/drivers/soc/mediatek/mtk-pm-domains.c >>>>> b/drivers/soc/mediatek/mtk-pm-domains.c >>>>> index 29e88adc8ea6..aa434f616fee 100644 >>>>> --- a/drivers/soc/mediatek/mtk-pm-domains.c >>>>> +++ b/drivers/soc/mediatek/mtk-pm-domains.c >>>> [...] >>>>> +/* >>>>> + * MT8183 power domain support >>>>> + */ >>>>> +static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { >>>>> + [MT8183_POWER_DOMAIN_AUDIO] = { >>>>> + .sta_mask = PWR_STATUS_AUDIO, >>>>> + .ctl_offs = 0x0314, >>>>> + .sram_pdn_bits = GENMASK(11, 8), >>>>> + .sram_pdn_ack_bits = GENMASK(15, 12), >>>>> + }, >>>>> + [MT8183_POWER_DOMAIN_CONN] = { >>>>> + .sta_mask = PWR_STATUS_CONN, >>>>> + .ctl_offs = 0x032c, >>>>> + .sram_pdn_bits = 0, >>>>> + .sram_pdn_ack_bits = 0, >>>>> + .bp_infracfg = { >>>>> + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, 0x2a0, 0x2a4, 0x228), >>>> >>>> We have repeating values triplets for set, clear and status register in infracfg >>>> and SMI. >>>> >>>> Weiyi can you help to get names to this registers? I wasn't able to find >>>> anything in the datasheet. >>> >>> I think for the infracfg part I figured it out: >>> >>> #define INFRA_TOPAXI_PROTECTEN_SET 0x2a0 >>> #define INFRA_TOPAXI_PROTECTEN_CLR 0x2a4 >>> #define INFRA_TOPAXI_PROTECTEN_STA1 0x228 >>> >>> #define INFRA_TOPAXI_PROTECTEN_1_SET 0x2a8 >>> #define INFRA_TOPAXI_PROTECTEN_1_CLR 0x2ac >>> #define INFRA_TOPAXI_PROTECTEN_STA1_1 0x258 >>> >>> #define INFRA_TOPAXI_PROTECTEN_MCU_SET 0x2d4 >>> #define INFRA_TOPAXI_PROTECTEN_MCU_CLR 0x2d8 >>> #define INFRA_TOPAXI_PROTECTEN_MM_STA1 0x2ec
These three should be: INFRA_TOPAXI_PROTECTEN_MM_SET 0x2d4 INFRA_TOPAXI_PROTECTEN_MM_CLR 0x2d8 INFRA_TOPAXI_PROTECTEN_MM_STA1 0x2ec
>>> > > I think this is SoC specific, right? So, I should add the MT8183_ prefix. >
It seems like in newer SoCs infracfg register map has changed the layout for INFRA_TOPAXI_PROTECTEN_SET and INFRA_TOPAXI_PROTECTEN_CLR registers. Apart from that it got expanded to be able to use bus protection on more HW blocks.
So not sure if MT8183_ is the right prefix. Maybe we should just rename INFRA_TOPAXI_PROTECTEN_SET to something like INFRA_TOPAXI_PROTECTEN_SET_V2 and do the same for INFRA_TOPAXI_PROTECTEN_CLR
Regards, Matthias
>>> Weiyi, can you still provide the register names for the SMI? >>> >>> Thanks in advance! >>> Matthias >>> >> Hi Matthias, >> >> SMI names are >> #define SMI_COMMON_CLAMP_EN 0x3c0 >> #define SMI_COMMON_CLAMP_EN_SET 0x3c4 >> #define SMI_COMMON_CLAMP_EN_CLR 0x3c8 >> > > The same here, this is specific for MT8183, right? > > Thanks, > Enric > >> Thanks >> >
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