Messages in this thread | | | Subject | Re: [PATCH 1/3] clk: keystone: sci-clk: fix parsing assigned-clock data during probe | From | Stephen Boyd <> | Date | Tue, 22 Sep 2020 12:59:14 -0700 |
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Quoting Tero Kristo (2020-09-07 01:57:38) > The DT clock probe loop incorrectly terminates after processing "clocks" > only, fix this by re-starting the loop when all entries for current > DT property have been parsed. > > Fixes: 8e48b33f9def ("clk: keystone: sci-clk: probe clocks from DT instead of firmware") > Reported-by: Peter Ujfalusi <peter.ujfalusi@ti.com> > Signed-off-by: Tero Kristo <t-kristo@ti.com> > ---
Applied to clk-next
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