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Subject[PATCH 1/5] arm64: spe: Allow new bits in SPE filter register
Date
The ARMv8.3-SPE extension adds some new bits for the event filter.

Remove bits 11, 17 and 18 from the RES0 mask, so they can be used
correctly.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm64/include/asm/sysreg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 554a7e8ecb07..efca4ee28671 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -281,7 +281,7 @@
#define SYS_PMSFCR_EL1_ST_SHIFT 18

#define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
-#define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL
+#define SYS_PMSEVFR_EL1_RES0 0x0000ffff00f90755UL

#define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
#define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0
--
2.17.1
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