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    Subject[PATCH v3 0/3] Repair Ingenic SoCs L2 cache capacity detection.
    Date
    1.The X1000E SoC has a 4-way L2 cache with a capacity of 128 KiB.
    The current code cannot detect its correctly, which will cause the
    CU1000-Neo board using the X1000E SoC to report that it has found
    a 5-way 320KiB L2 cache at boot time.
    2.The JZ4775 SoC has a 4-way L2 cache with a capacity of 256 KiB.
    The current code cannot detect its correctly, which will cause the
    Mensa board using the JZ4775 SoC to report that it has found a 5-way
    320KiB L2 cache at boot time.

    This series of patches is to fix this problem.

    v2->v3:
    Fix the warning that appears when running checkpatch, add relevant
    compatible string.

    周琰杰 (Zhou Yanjie) (3):
    dt-bindings: MIPS: Add X2000E based CU2000-Neo.
    MIPS: Ingenic: Add system type for new Ingenic SoCs.
    MIPS: Ingenic: Fix bugs when detecting L2 cache of JZ4775 and X1000E.

    Documentation/devicetree/bindings/mips/ingenic/devices.yaml | 5 +++++
    arch/mips/generic/board-ingenic.c | 12 ++++++++++++
    arch/mips/include/asm/bootinfo.h | 2 ++
    arch/mips/mm/sc-mips.c | 2 ++
    4 files changed, 21 insertions(+)

    --
    2.11.0

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