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    Subject[PATCHv8 07/12] PCI: layerscape: Modify the way of getting capability with different PEX
    Date
    From: Xiaowei Bao <xiaowei.bao@nxp.com>

    The different PCIe controller in one board may be have different
    capability of MSI or MSIX, so change the way of getting the MSI
    capability, make it more flexible.

    Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
    Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
    Reviewed-by: Rob Herring <robh@kernel.org>
    ---
    V8:
    - No change.

    .../pci/controller/dwc/pci-layerscape-ep.c | 31 ++++++++++++++-----
    1 file changed, 23 insertions(+), 8 deletions(-)

    diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
    index 0691d9ad1356..9601f9c09cb1 100644
    --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
    +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
    @@ -22,6 +22,7 @@

    struct ls_pcie_ep {
    struct dw_pcie *pci;
    + struct pci_epc_features *ls_epc;
    };

    #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
    @@ -40,26 +41,31 @@ static const struct of_device_id ls_pcie_ep_of_match[] = {
    { },
    };

    -static const struct pci_epc_features ls_pcie_epc_features = {
    - .linkup_notifier = false,
    - .msi_capable = true,
    - .msix_capable = false,
    - .bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4),
    -};
    -
    static const struct pci_epc_features*
    ls_pcie_ep_get_features(struct dw_pcie_ep *ep)
    {
    - return &ls_pcie_epc_features;
    + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
    + struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
    +
    + return pcie->ls_epc;
    }

    static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
    {
    struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
    + struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
    + struct dw_pcie_ep_func *ep_func;
    enum pci_barno bar;

    + ep_func = dw_pcie_ep_get_func_from_ep(ep, 0);
    + if (!ep_func)
    + return;
    +
    for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
    dw_pcie_ep_reset_bar(pci, bar);
    +
    + pcie->ls_epc->msi_capable = ep_func->msi_cap ? true : false;
    + pcie->ls_epc->msix_capable = ep_func->msix_cap ? true : false;
    }

    static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
    @@ -119,6 +125,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
    struct device *dev = &pdev->dev;
    struct dw_pcie *pci;
    struct ls_pcie_ep *pcie;
    + struct pci_epc_features *ls_epc;
    struct resource *dbi_base;
    int ret;

    @@ -130,6 +137,10 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
    if (!pci)
    return -ENOMEM;

    + ls_epc = devm_kzalloc(dev, sizeof(*ls_epc), GFP_KERNEL);
    + if (!ls_epc)
    + return -ENOMEM;
    +
    dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
    pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
    if (IS_ERR(pci->dbi_base))
    @@ -140,6 +151,10 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
    pci->ops = &ls_pcie_ep_ops;
    pcie->pci = pci;

    + ls_epc->bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4),
    +
    + pcie->ls_epc = ls_epc;
    +
    platform_set_drvdata(pdev, pcie);

    ret = ls_add_pcie_ep(pcie, pdev);
    --
    2.17.1
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