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SubjectRe: [PATCH v2 25/37] arm64: kasan: Enable in-kernel MTE
On Tue, Sep 15, 2020 at 11:16:07PM +0200, Andrey Konovalov wrote:
> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> index 23c326a06b2d..5ba7ac5e9c77 100644
> --- a/arch/arm64/mm/proc.S
> +++ b/arch/arm64/mm/proc.S
> @@ -427,6 +427,10 @@ SYM_FUNC_START(__cpu_setup)
> */
> mov_q x5, MAIR_EL1_SET
> #ifdef CONFIG_ARM64_MTE
> + mte_present .req x20
> +
> + mov mte_present, #0
> +
> /*
> * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported
> * (ID_AA64PFR1_EL1[11:8] > 1).
> @@ -447,6 +451,8 @@ SYM_FUNC_START(__cpu_setup)
> /* clear any pending tag check faults in TFSR*_EL1 */
> msr_s SYS_TFSR_EL1, xzr
> msr_s SYS_TFSRE0_EL1, xzr
> +
> + mov mte_present, #1
> 1:
> #endif
> msr mair_el1, x5
> @@ -485,6 +491,13 @@ SYM_FUNC_START(__cpu_setup)
> orr x10, x10, #TCR_HA // hardware Access flag update
> 1:
> #endif /* CONFIG_ARM64_HW_AFDBM */
> +#ifdef CONFIG_ARM64_MTE
> + /* Update TCR_EL1 if MTE is supported (ID_AA64PFR1_EL1[11:8] > 1) */
> + cbz mte_present, 1f
> + orr x10, x10, #SYS_TCR_EL1_TCMA1
> +1:
> + .unreq mte_present
> +#endif
> msr tcr_el1, x10
> /*
> * Prepare SCTLR

I'd keep this simpler, no branches or #ifdefs (you can still add the
.req if you want):

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 23c326a06b2d..a35344754081 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -426,6 +426,7 @@ SYM_FUNC_START(__cpu_setup)
* Memory region attributes
*/
mov_q x5, MAIR_EL1_SET
+ mov x8, #0
#ifdef CONFIG_ARM64_MTE
/*
* Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported
@@ -447,6 +448,9 @@ SYM_FUNC_START(__cpu_setup)
/* clear any pending tag check faults in TFSR*_EL1 */
msr_s SYS_TFSR_EL1, xzr
msr_s SYS_TFSRE0_EL1, xzr
+
+ /* set the TCR_EL1 bits */
+ orr x8, x8, #SYS_TCR_EL1_TCMA1
1:
#endif
msr mair_el1, x5
@@ -457,6 +461,7 @@ SYM_FUNC_START(__cpu_setup)
mov_q x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS
+ orr x10, x10, x8
tcr_clear_errata_bits x10, x9, x5

#ifdef CONFIG_ARM64_VA_BITS_52
--
Catalin

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