lkml.org 
[lkml]   [2020]   [Sep]   [17]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH AUTOSEL 5.4 223/330] drm/amdgpu/vcn2.0: stall DPG when WPTR/RPTR reset
    Date
    From: James Zhu <James.Zhu@amd.com>

    [ Upstream commit ef563ff403404ef2f234abe79bdd9f04ab6481c9 ]

    Add vcn dpg harware synchronization to fix race condition
    issue between vcn driver and hardware.

    Signed-off-by: James Zhu <James.Zhu@amd.com>
    Reviewed-by: Leo Liu <leo.liu@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 16 ++++++++++++++++
    1 file changed, 16 insertions(+)

    diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
    index 36ad0c0e8efbc..cd2cbe760e883 100644
    --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
    +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
    @@ -1026,6 +1026,10 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
    tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
    WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);

    + /* Stall DPG before WPTR/RPTR reset */
    + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
    + UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
    + ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
    /* set the write pointer delay */
    WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);

    @@ -1048,6 +1052,9 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
    WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
    lower_32_bits(ring->wptr));

    + /* Unstall DPG */
    + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
    + 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
    return 0;
    }

    @@ -1357,8 +1364,13 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
    UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
    UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);

    + /* Stall DPG before WPTR/RPTR reset */
    + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
    + UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
    + ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
    /* Restore */
    ring = &adev->vcn.inst->ring_enc[0];
    + ring->wptr = 0;
    WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
    WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
    WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
    @@ -1366,6 +1378,7 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
    WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

    ring = &adev->vcn.inst->ring_enc[1];
    + ring->wptr = 0;
    WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
    WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
    WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
    @@ -1374,6 +1387,9 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,

    WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
    RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
    + /* Unstall DPG */
    + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
    + 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);

    SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
    UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
    --
    2.25.1
    \
     
     \ /
      Last update: 2020-09-18 04:06    [W:2.355 / U:0.504 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site