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Subject[RESEND 1/3] mmc: dt-bindings: add support for MT8192 SoC
Date
MT8192 mmc host ip is compatible with MT8183.
Add support for this.

Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
---
Documentation/devicetree/bindings/mmc/mtk-sd.txt | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
index 26a8f320a156..6422ad7d439d 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
@@ -10,7 +10,7 @@ Required properties:
- compatible: value should be either of the following.
"mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
- "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
+ "mediatek,mt8192-mmc", "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
"mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
"mediatek,mt6779-mmc": for mmc host ip compatible with mt6779
"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
@@ -27,6 +27,10 @@ Required properties:
"hclk" - HCLK which used for host (required)
"source_cg" - independent source clock gate (required for MT2712)
"bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3)
+ "sys_cg" - msdc subsys clock gate (required for MT8192)
+ "pclk_cg" - peripheral bus clock gate (required for MT8192)
+ "axi_cg" - AXI bus clock gate (required for MT8192)
+ "ahb_cg" - AHB bus clock gate (required for MT8192)
- pinctrl-names: should be "default", "state_uhs"
- pinctrl-0: should contain default/high speed pin ctrl
- pinctrl-1: should contain uhs mode pin ctrl
--
2.18.0
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