Messages in this thread | | | Date | Tue, 15 Sep 2020 15:47:57 +0100 | From | Marc Zyngier <> | Subject | Re: [PATCH] irqchip/gic-v4.1: Optimize the delay time of the poll on the GICR_VPENDBASER.Dirty bit |
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On 2020-09-15 15:04, lushenming wrote: > Thanks for your quick response. > > Okay, I agree that busy-waiting may add more overhead at the RD level. > But I think that the delay time can be adjusted. In our latest > hardware implementation, we optimize the search of the VPT, now even > the VPT full of interrupts (56k) can be parsed within 2 microseconds.
It's not so much when the VPT is full that it is bad. It is when the pending interrupts are not cached, and that you don't know *where* to look for them in the VPT.
> It is true that the parse speeds of various hardware are different, > but does directly waiting for 10 microseconds make the optimization of > those fast hardware be completely masked? Maybe we can set the delay > time smaller, like 1 microseconds?
That certainly would be more acceptable. But I still question the impact of such a change compared to the cost of a vcpu entry. I suggest you come up with measurements that actually show that polling this register more often significantly reduces the entry latency. Only then can we make an educated decision.
Thanks,
M. -- Jazz is not dead. It just smells funny...
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