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Subject[PATCH v3 0/7] SM8150 and SM8250 dispcc drivers
Date
Add display clock drivers required to get DSI and DP displays working on
SM8150 and SM8250 SoCs.

Derived from downstream drivers. Notable changes compared to downstream:
- EDP clks removed (nothing uses these even in downstream it seems)
- freq_tbl values for dp_link clk is in Hz and not kHz

v2:
- updated dts example to reflect the change (first patch)
- updated config_ctl_hi1_val in sm8250 dispcc to latest downstream

v3:
- combined dt-binding: "gcc_disp_gpll0_clk_src" is needed by sc7180 too
- use the right order in drivers/clk/qcom/Kconfig

Jonathan Marek (7):
dt-bindings: clock: sdm845-dispcc: same name for dp_phy clocks as
sc7180
arm64: dts: qcom: sdm845-dispcc: same name for dp_phy clocks as sc7180
dt-bindings: clock: combine qcom,sdm845-dispcc and qcom,sc7180-dispcc
dt-bindings: clock: Introduce QCOM SM8150 display clock bindings
dt-bindings: clock: Introduce QCOM SM8250 display clock bindings
clk: qcom: Add display clock controller driver for SM8150
clk: qcom: Add display clock controller driver for SM8250

...om,sdm845-dispcc.yaml => qcom,dispcc.yaml} | 32 +-
.../bindings/clock/qcom,sc7180-dispcc.yaml | 86 --
arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 +-
drivers/clk/qcom/Kconfig | 18 +
drivers/clk/qcom/Makefile | 2 +
drivers/clk/qcom/dispcc-sm8150.c | 1152 +++++++++++++++++
drivers/clk/qcom/dispcc-sm8250.c | 1100 ++++++++++++++++
.../dt-bindings/clock/qcom,dispcc-sm8150.h | 69 +
.../dt-bindings/clock/qcom,dispcc-sm8250.h | 66 +
9 files changed, 2430 insertions(+), 99 deletions(-)
rename Documentation/devicetree/bindings/clock/{qcom,sdm845-dispcc.yaml => qcom,dispcc.yaml} (74%)
delete mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
create mode 100644 drivers/clk/qcom/dispcc-sm8150.c
create mode 100644 drivers/clk/qcom/dispcc-sm8250.c
create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8150.h
create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8250.h

--
2.26.1

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