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Subject[PATCH v3 00/16] arm/arm64: Turning IPIs into normal interrupts
Date
For as long as SMP ARM has existed, IPIs have been handled as
something special. The arch code and the interrupt controller exchange
a couple of hooks (one to generate an IPI, another to handle it).

Although this is perfectly manageable, it prevents the use of features
that we could use if IPIs were Linux IRQs (such as pseudo-NMIs). It
also means that each interrupt controller driver has to follow an
architecture-specific interface instead of just implementing the base
irqchip functionalities. The arch code also duplicates a number of
things that the core irq code already does (such as calling
set_irq_regs(), irq_enter()...).

This series tries to remedy this on arm/arm64 by offering a new
registration interface where the irqchip gives the arch code a range
of interrupts to use for IPIs. The arch code requests these as normal
per-cpu interrupts.

The bulk of the work is at the interrupt controller level, where all 5
irqchips used on arm+SMP/arm64 get converted.

Finally, we drop the legacy registration interface as well as the
custom statistics accounting.

Note that I have had a look at providing a "generic" interface by
expanding the kernel/irq/ipi.c bag of helpers, but so far all
irqchips have very different requirements, so there is hardly anything
to consolidate for now. Maybe some as hip04 and the Marvell horror get
cleaned up (the latter certainly could do with a good dusting).

This has been tested on a bunch of 32 and 64bit guests (GICv2, GICv3),
as well as 64bit bare metal (GICv3). The RPi part has only been tested
in QEMU as a 64bit guest, while the HiSi and Marvell parts have only
been compile-tested.

I'm aiming for 5.10 for this, so any comment would be appreciated.

* From v2:
- Tidied up the arch code (__read_mostly for the IPI handling data,
WARN_ON_ONCE on setup and teardown), dropped spurious prototype
on 32bit
- Prevent IPIs from being forwarded to VCPUs
- Merged the GIC affinity fix, hence one less patch
- Added RBs from Valentin

* From v1:
- Clarified the effect of nesting irq_enter/exit (Russell)
- Changed the point where we tear IPIs down on (Valentin)
- IPIs are no longer accessible from DT
- HIP04 and Armada 370-XP have been converted, but are untested
- arch-specific kstat accounting is removed
- ARM's legacy interface is dropped

Marc Zyngier (16):
genirq: Add fasteoi IPI flow
genirq: Allow interrupts to be excluded from /proc/interrupts
arm64: Allow IPIs to be handled as normal interrupts
ARM: Allow IPIs to be handled as normal interrupts
irqchip/gic-v3: Describe the SGI range
irqchip/gic-v3: Configure SGIs as standard interrupts
irqchip/gic: Refactor SMP configuration
irqchip/gic: Configure SGIs as standard interrupts
irqchip/gic-common: Don't enable SGIs by default
irqchip/bcm2836: Configure mailbox interrupts as standard interrupts
irqchip/hip04: Configure IPIs as standard interrupts
irqchip/armada-370-xp: Configure IPIs as standard interrupts
arm64: Kill __smp_cross_call and co
arm64: Remove custom IRQ stat accounting
ARM: Kill __smp_cross_call and co
ARM: Remove custom IRQ stat accounting

arch/arm/Kconfig | 1 +
arch/arm/include/asm/hardirq.h | 17 --
arch/arm/include/asm/smp.h | 5 +-
arch/arm/kernel/smp.c | 135 +++++++++-----
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/hardirq.h | 9 -
arch/arm64/include/asm/irq_work.h | 4 +-
arch/arm64/include/asm/smp.h | 6 +-
arch/arm64/kernel/smp.c | 121 ++++++++-----
drivers/irqchip/irq-armada-370-xp.c | 262 +++++++++++++++++++---------
drivers/irqchip/irq-bcm2836.c | 151 +++++++++++++---
drivers/irqchip/irq-gic-common.c | 3 -
drivers/irqchip/irq-gic-v3.c | 104 ++++++-----
drivers/irqchip/irq-gic.c | 177 +++++++++++--------
drivers/irqchip/irq-hip04.c | 89 +++++-----
include/linux/irq.h | 5 +-
kernel/irq/chip.c | 27 +++
kernel/irq/debugfs.c | 1 +
kernel/irq/proc.c | 2 +-
kernel/irq/settings.h | 7 +
20 files changed, 720 insertions(+), 407 deletions(-)

--
2.27.0

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