Messages in this thread | | | Subject | Re: [PATCH v9 2/3] drm: bridge: Add support for Cadence MHDP8546 DPI/DP bridge | From | Tomi Valkeinen <> | Date | Tue, 1 Sep 2020 11:34:45 +0300 |
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Hi Swapnil,
On 31/08/2020 11:23, Swapnil Jakhade wrote:
> + line_thresh1 = ((vs + 1) << 5) * 8 / bpp; > + line_thresh2 = (pxlclock << 5) / 1000 / rate * (vs + 1) - (1 << 5); > + line_thresh = line_thresh1 - line_thresh2 / mhdp->link.num_lanes; > + line_thresh = (line_thresh >> 5) + 2;
These calculations do not seem to go correctly. There's no comment what's the logic here, but e.g. for 640x480 (pxlclock 31500) with 1.62Gbps link, I get vs=4, and then the second line above comes to:
(31500 << 5) / 1000 / 162 * (4+1) - (1<<5) = -0.8888888888888893
The result is line_thresh of 100663299.
Tomi
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