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    Subject[RESEND v7, PATCH 7/7] arm64: dts: add display nodes for mt8183
    Date
    This patch add display nodes for mt8183

    Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
    ---
    arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98 ++++++++++++++++++++++++++++++++
    1 file changed, 98 insertions(+)

    diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
    index 7b781eb..440cf22 100644
    --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
    +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
    @@ -31,6 +31,11 @@
    i2c9 = &i2c9;
    i2c10 = &i2c10;
    i2c11 = &i2c11;
    + ovl0 = &ovl0;
    + ovl_2l0 = &ovl_2l0;
    + ovl_2l1 = &ovl_2l1;
    + rdma0 = &rdma0;
    + rdma1 = &rdma1;
    };

    cpus {
    @@ -707,9 +712,102 @@
    mmsys: syscon@14000000 {
    compatible = "mediatek,mt8183-mmsys", "syscon";
    reg = <0 0x14000000 0 0x1000>;
    + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
    #clock-cells = <1>;
    };

    + ovl0: ovl@14008000 {
    + compatible = "mediatek,mt8183-disp-ovl";
    + reg = <0 0x14008000 0 0x1000>;
    + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
    + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
    + clocks = <&mmsys CLK_MM_DISP_OVL0>;
    + };
    +
    + ovl_2l0: ovl@14009000 {
    + compatible = "mediatek,mt8183-disp-ovl-2l";
    + reg = <0 0x14009000 0 0x1000>;
    + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
    + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
    + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
    + };
    +
    + ovl_2l1: ovl@1400a000 {
    + compatible = "mediatek,mt8183-disp-ovl-2l";
    + reg = <0 0x1400a000 0 0x1000>;
    + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
    + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
    + clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
    + };
    +
    + rdma0: rdma@1400b000 {
    + compatible = "mediatek,mt8183-disp-rdma";
    + reg = <0 0x1400b000 0 0x1000>;
    + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
    + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
    + clocks = <&mmsys CLK_MM_DISP_RDMA0>;
    + mediatek,rdma_fifo_size = <5120>;
    + };
    +
    + rdma1: rdma@1400c000 {
    + compatible = "mediatek,mt8183-disp-rdma";
    + reg = <0 0x1400c000 0 0x1000>;
    + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
    + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
    + clocks = <&mmsys CLK_MM_DISP_RDMA1>;
    + mediatek,rdma_fifo_size = <2048>;
    + };
    +
    + color0: color@1400e000 {
    + compatible = "mediatek,mt8183-disp-color",
    + "mediatek,mt8173-disp-color";
    + reg = <0 0x1400e000 0 0x1000>;
    + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
    + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
    + clocks = <&mmsys CLK_MM_DISP_COLOR0>;
    + };
    +
    + ccorr0: ccorr@1400f000 {
    + compatible = "mediatek,mt8183-disp-ccorr";
    + reg = <0 0x1400f000 0 0x1000>;
    + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
    + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
    + clocks = <&mmsys CLK_MM_DISP_CCORR0>;
    + };
    +
    + aal0: aal@14010000 {
    + compatible = "mediatek,mt8183-disp-aal",
    + "mediatek,mt8173-disp-aal";
    + reg = <0 0x14010000 0 0x1000>;
    + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
    + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
    + clocks = <&mmsys CLK_MM_DISP_AAL0>;
    + };
    +
    + gamma0: gamma@14011000 {
    + compatible = "mediatek,mt8183-disp-gamma",
    + "mediatek,mt8173-disp-gamma";
    + reg = <0 0x14011000 0 0x1000>;
    + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
    + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
    + clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
    + };
    +
    + dither0: dither@14012000 {
    + compatible = "mediatek,mt8183-disp-dither";
    + reg = <0 0x14012000 0 0x1000>;
    + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
    + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
    + clocks = <&mmsys CLK_MM_DISP_DITHER0>;
    + };
    +
    + mutex: mutex@14016000 {
    + compatible = "mediatek,mt8183-disp-mutex";
    + reg = <0 0x14016000 0 0x1000>;
    + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
    + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
    + };
    +
    smi_common: smi@14019000 {
    compatible = "mediatek,mt8183-smi-common", "syscon";
    reg = <0 0x14019000 0 0x1000>;
    --
    1.8.1.1.dirty
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