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    SubjectRe: [PATCH v1 2/2] perf/core: Fake regs for leaked kernel samples
    On Thu, Aug 06, 2020 at 11:18:27AM +0200, peterz@infradead.org wrote:

    > Suppose we have nested virt:
    >
    > L0-hv
    > |
    > G0/L1-hv
    > |
    > G1
    >
    > And we're running in G0, then:
    >
    > - 'exclude_hv' would exclude L0 events
    > - 'exclude_host' would ... exclude L1-hv events?
    > - 'exclude_guest' would ... exclude G1 events?

    So in arch/x86/events/intel/core.c we have:

    static inline void intel_set_masks(struct perf_event *event, int idx)
    {
    struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

    if (event->attr.exclude_host)
    __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
    if (event->attr.exclude_guest)
    __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
    if (event_is_checkpointed(event))
    __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
    }

    which is, afaict, just plain wrong. Should that not be something like:

    if (!event->attr.exclude_host)
    __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
    if (!event->attr.exclude_guest)
    __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);


    Also, ARM64 seems to also implement this stuff, Mark, do you have any
    insight on how all this is 'supposed' to work?

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