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    Subject[PATCH v6 09/76] x86/umip: Factor out instruction decoding
    Date
    From: Joerg Roedel <jroedel@suse.de>

    Factor out the code used to decode an instruction with the correct
    address and operand sizes to a helper function.

    No functional changes.

    Signed-off-by: Joerg Roedel <jroedel@suse.de>
    Link: https://lore.kernel.org/r/20200724160336.5435-9-joro@8bytes.org
    ---
    arch/x86/include/asm/insn-eval.h | 2 ++
    arch/x86/kernel/umip.c | 23 +---------------
    arch/x86/lib/insn-eval.c | 45 ++++++++++++++++++++++++++++++++
    3 files changed, 48 insertions(+), 22 deletions(-)

    diff --git a/arch/x86/include/asm/insn-eval.h b/arch/x86/include/asm/insn-eval.h
    index b8b9ef1bbd06..392b4fe377f9 100644
    --- a/arch/x86/include/asm/insn-eval.h
    +++ b/arch/x86/include/asm/insn-eval.h
    @@ -21,5 +21,7 @@ unsigned long insn_get_seg_base(struct pt_regs *regs, int seg_reg_idx);
    int insn_get_code_seg_params(struct pt_regs *regs);
    int insn_fetch_from_user(struct pt_regs *regs,
    unsigned char buf[MAX_INSN_SIZE]);
    +bool insn_decode(struct insn *insn, struct pt_regs *regs,
    + unsigned char buf[MAX_INSN_SIZE], int buf_size);

    #endif /* _ASM_X86_INSN_EVAL_H */
    diff --git a/arch/x86/kernel/umip.c b/arch/x86/kernel/umip.c
    index ad135be4f1f0..f6225bf22c02 100644
    --- a/arch/x86/kernel/umip.c
    +++ b/arch/x86/kernel/umip.c
    @@ -342,7 +342,6 @@ bool fixup_umip_exception(struct pt_regs *regs)
    unsigned long *reg_addr;
    void __user *uaddr;
    struct insn insn;
    - int seg_defs;

    if (!regs)
    return false;
    @@ -357,27 +356,7 @@ bool fixup_umip_exception(struct pt_regs *regs)
    if (!nr_copied)
    return false;

    - insn_init(&insn, buf, nr_copied, user_64bit_mode(regs));
    -
    - /*
    - * Override the default operand and address sizes with what is specified
    - * in the code segment descriptor. The instruction decoder only sets
    - * the address size it to either 4 or 8 address bytes and does nothing
    - * for the operand bytes. This OK for most of the cases, but we could
    - * have special cases where, for instance, a 16-bit code segment
    - * descriptor is used.
    - * If there is an address override prefix, the instruction decoder
    - * correctly updates these values, even for 16-bit defaults.
    - */
    - seg_defs = insn_get_code_seg_params(regs);
    - if (seg_defs == -EINVAL)
    - return false;
    -
    - insn.addr_bytes = INSN_CODE_SEG_ADDR_SZ(seg_defs);
    - insn.opnd_bytes = INSN_CODE_SEG_OPND_SZ(seg_defs);
    -
    - insn_get_length(&insn);
    - if (nr_copied < insn.length)
    + if (!insn_decode(&insn, regs, buf, nr_copied))
    return false;

    umip_inst = identify_insn(&insn);
    diff --git a/arch/x86/lib/insn-eval.c b/arch/x86/lib/insn-eval.c
    index 0c4f7ebc261b..f52046f90dd3 100644
    --- a/arch/x86/lib/insn-eval.c
    +++ b/arch/x86/lib/insn-eval.c
    @@ -1407,3 +1407,48 @@ int insn_fetch_from_user(struct pt_regs *regs, unsigned char buf[MAX_INSN_SIZE])

    return MAX_INSN_SIZE - not_copied;
    }
    +
    +/**
    + * insn_decode() - Decode an instruction
    + * @insn: Structure to store decoded instruction
    + * @regs: Structure with register values as seen when entering kernel mode
    + * @buf: Buffer containing the instruction bytes
    + * @buf_size: Number of instruction bytes available in buf
    + *
    + * Decodes the instruction provided in buf and stores the decoding results in
    + * insn. Also determines the correct address and operand sizes.
    + *
    + * Returns:
    + *
    + * True if instruction was decoded, False otherwise.
    + */
    +bool insn_decode(struct insn *insn, struct pt_regs *regs,
    + unsigned char buf[MAX_INSN_SIZE], int buf_size)
    +{
    + int seg_defs;
    +
    + insn_init(insn, buf, buf_size, user_64bit_mode(regs));
    +
    + /*
    + * Override the default operand and address sizes with what is specified
    + * in the code segment descriptor. The instruction decoder only sets
    + * the address size it to either 4 or 8 address bytes and does nothing
    + * for the operand bytes. This OK for most of the cases, but we could
    + * have special cases where, for instance, a 16-bit code segment
    + * descriptor is used.
    + * If there is an address override prefix, the instruction decoder
    + * correctly updates these values, even for 16-bit defaults.
    + */
    + seg_defs = insn_get_code_seg_params(regs);
    + if (seg_defs == -EINVAL)
    + return false;
    +
    + insn->addr_bytes = INSN_CODE_SEG_ADDR_SZ(seg_defs);
    + insn->opnd_bytes = INSN_CODE_SEG_OPND_SZ(seg_defs);
    +
    + insn_get_length(insn);
    + if (buf_size < insn->length)
    + return false;
    +
    + return true;
    +}
    --
    2.28.0
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