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    Subject[PATCH AUTOSEL 5.4 15/38] drm/amd/powerplay: correct UVD/VCE PG state on custom pptable uploading
    Date
    From: Evan Quan <evan.quan@amd.com>

    [ Upstream commit 2c5b8080d810d98e3e59617680218499b17c84a1 ]

    The UVD/VCE PG state is managed by UVD and VCE IP. It's error-prone to
    assume the bootup state in SMU based on the dpm status.

    Signed-off-by: Evan Quan <evan.quan@amd.com>
    Acked-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 6 ------
    1 file changed, 6 deletions(-)

    diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
    index 08b91c31532ba..947e4fa3c5e68 100644
    --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
    +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
    @@ -1640,12 +1640,6 @@ static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)

    data->uvd_power_gated = true;
    data->vce_power_gated = true;
    -
    - if (data->smu_features[GNLD_DPM_UVD].enabled)
    - data->uvd_power_gated = false;
    -
    - if (data->smu_features[GNLD_DPM_VCE].enabled)
    - data->vce_power_gated = false;
    }

    static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
    --
    2.25.1
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