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Subject[PATCH 1/2] dt-bindings: PCI: sprd: Document Unisoc PCIe RC host controller
Date
From: Billows Wu <billows.wu@unisoc.com>

This series adds PCIe bindings for Uisoc SoCs.
This controller is based on DesignWare PCIe IP.

Signed-off-by: Billows Wu <billows.wu@unisoc.com>
---
.../devicetree/bindings/pci/sprd-pcie.yaml | 88 ++++++++++++++++++++++
1 file changed, 88 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/sprd-pcie.yaml

diff --git a/Documentation/devicetree/bindings/pci/sprd-pcie.yaml b/Documentation/devicetree/bindings/pci/sprd-pcie.yaml
new file mode 100644
index 0000000..6eab4b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/sprd-pcie.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/sprd-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SoC PCIe Host Controller Device Tree Bindings
+
+maintainers:
+ - Billows Wu <billows.wu@unisoc.com>
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+ - $ref: "sprd-pcie.yaml#"
+
+properties:
+ compatible:
+ items:
+ - const: sprd,pcie
+ - const: sprd,pcie-ep
+
+ reg:
+ minItems: 2
+ maxItems: 3
+ items:
+ - description: Controller control and status registers.
+ - description: PCIe shadow registers.
+ - description: PCIe configuration registers.
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: dbi2
+ - const: cfg
+
+ ranges:
+ maxItems: 2
+
+ num-lanes:
+ maxItems: 1
+ description: Number of lanes to use for this port.
+
+ num-ib-windows:
+ maxItems: 1
+ description: Number of inbound windows to use for this port.
+
+ num-ob-windows:
+ maxItems: 1
+ description: Number of outbound windows to use for this port.
+
+ bus-range:
+ description: Range of bus numbers associated with this controller.
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - num-lanes
+ - ranges
+ - bus-range
+ - interrupts
+ - interrupt-names
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ pcie0@2b100000 {
+ compatible = "sprd,pcie", "snps,dw-pcie";
+ reg = <0x0 0x2b100000 0x0 0x2000>,
+ <0x2 0x00000000 0x0 0x2000>;
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x01000000 0x0 0x00000000 0x2 0x00002000 0x0 0x00010000
+ 0x03000000 0x0 0x10000000 0x2 0x10000000 0x1 0xefffffff>;
+ bus-range = <0 15>;
+ num-lanes = <1>;
+ num-viewport = <8>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ };
--
2.7.4
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