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    Subject[PATCH 5.8 165/232] clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk
    Date
    From: Konrad Dybcio <konradybcio@gmail.com>

    [ Upstream commit 3386af51d3bcebcba3f7becdb1ef2e384abe90cf ]

    Add missing halt_check, hwcg_reg and hwcg_bit properties.
    These were likely omitted when porting the driver upstream.

    Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
    Link: https://lore.kernel.org/r/20200726111215.22361-9-konradybcio@gmail.com
    Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660")
    Signed-off-by: Stephen Boyd <sboyd@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/qcom/gcc-sdm660.c | 3 +++
    1 file changed, 3 insertions(+)

    diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
    index bf5730832ef3d..c6fb57cd576f5 100644
    --- a/drivers/clk/qcom/gcc-sdm660.c
    +++ b/drivers/clk/qcom/gcc-sdm660.c
    @@ -1715,6 +1715,9 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {

    static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
    .halt_reg = 0x8a004,
    + .halt_check = BRANCH_HALT,
    + .hwcg_reg = 0x8a004,
    + .hwcg_bit = 1,
    .clkr = {
    .enable_reg = 0x8a004,
    .enable_mask = BIT(0),
    --
    2.25.1


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