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SubjectRe: [PATCH 6/8] arm64: dts: renesas: Initial r8a774e1 SoC device tree
Hi Marc,

Thank you for the review.

On Wed, Jul 8, 2020 at 6:53 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On 2020-07-08 18:48, Lad Prabhakar wrote:
> > From: Marian-Cristian Rotariu
> > <marian-cristian.rotariu.rb@bp.renesas.com>
> >
> > Basic support for the RZ/G2H SoC.
> >
> > Signed-off-by: Marian-Cristian Rotariu
> > <marian-cristian.rotariu.rb@bp.renesas.com>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 652 ++++++++++++++++++++++
> > 1 file changed, 652 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> > b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
> > new file mode 100644
> > index 000000000000..6637e157ffcd
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
>
> [...]
> > + gic: interrupt-controller@f1010000 {
> > + compatible = "arm,gic-400";
> > + #interrupt-cells = <3>;
> > + #address-cells = <0>;
> > + interrupt-controller;
> > + reg = <0x0 0xf1010000 0 0x1000>,
> > + <0x0 0xf1020000 0 0x20000>,
> > + <0x0 0xf1040000 0 0x20000>,
> > + <0x0 0xf1060000 0 0x20000>;
> > + interrupts = <GIC_PPI 9
> > + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
>
> You seem to have a bit more than only 2 CPUs in this system.
>
Argh should be 8.

Cheers,
--Prabhakar

> > + clocks = <&cpg CPG_MOD 408>;
> > + clock-names = "clk";
> > + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
> > + resets = <&cpg 408>;
> > + };
>
> M.
> --
> Jazz is not dead. It just smells funny...

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