Messages in this thread | | | Subject | Re: [RFC PATCH 09/14] coresight: etm4x: Add sysreg access helpers | From | Suzuki K Poulose <> | Date | Fri, 31 Jul 2020 10:51:08 +0100 |
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On 07/30/2020 10:41 PM, Mathieu Poirier wrote: > On Wed, Jul 22, 2020 at 06:20:35PM +0100, Suzuki K Poulose wrote: >> ETMv4.4 architecture defines the system instructions for accessing >> ETM via register accesses. Add basic support for accessing a given >> register via system instructions. >> >> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> >> Cc: Mike Leach <mike.leach@linaro.org> >> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> >> --- >> drivers/hwtracing/coresight/coresight-etm4x.c | 39 ++ >> drivers/hwtracing/coresight/coresight-etm4x.h | 379 ++++++++++++++++-- >> 2 files changed, 394 insertions(+), 24 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
>> static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct csdev_access *csa) >> { >> /* Writing 0 to TRCOSLAR unlocks the trace registers */ >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h >> index 2b51d03ab6d7..f5d708206339 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x.h >> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
0x1FC >> -/* Resource selection registers */ >> +/* >> + * Resource selection registers, n = 2-31. >> + * First pair (regs 0, 1) is always present and is reserved. >> + */ >> #define TRCRSCTLRn(n) (0x200 + (n * 4)) >> -/* Single-shot comparator registers */ >> +/* Single-shot comparator registers, n = 0-7 */ >> #define TRCSSCCRn(n) (0x280 + (n * 4)) >> #define TRCSSCSRn(n) (0x2A0 + (n * 4)) >> #define TRCSSPCICRn(n) (0x2C0 + (n * 4)) >> @@ -80,11 +83,13 @@ >> #define TRCPDCR 0x310 >> #define TRCPDSR 0x314 >> /* Trace registers (0x318-0xEFC) */ >> -/* Comparator registers */ >> +/* Address Comparator registers n = 0-15 */ >> #define TRCACVRn(n) (0x400 + (n * 8)) >> #define TRCACATRn(n) (0x480 + (n * 8)) >> +/* Data Value Comparator Value registers, n = 0-7 */ >> #define TRCDVCVRn(n) (0x500 + (n * 16)) >> #define TRCDVCMRn(n) (0x580 + (n * 16)) >> +/* ContextID/Virtual ContextID comparators, n = 0-7 */ > > Extra documentation is good but it has to be in a separate patch. >
Sure, will split this. It was partly for making sure that I don't miss a case for a register in the list.
Cheers Suzuki
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