Messages in this thread | | | From | Valentin Schneider <> | Subject | Re: [PATCH v4 09/10] Powerpc/smp: Create coregroup domain | Date | Tue, 28 Jul 2020 16:03:11 +0100 |
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Hi,
On 27/07/20 06:32, Srikar Dronamraju wrote: > Add percpu coregroup maps and masks to create coregroup domain. > If a coregroup doesn't exist, the coregroup domain will be degenerated > in favour of SMT/CACHE domain. >
So there's at least one arm64 platform out there with the same "pairs of cores share L2" thing (Ampere eMAG), and that lives quite happily with the default scheduler topology (SMT/MC/DIE). Each pair of core gets its MC domain, and the whole system is covered by DIE.
Now arguably it's not a perfect representation; DIE doesn't have SD_SHARE_PKG_RESOURCES so the highest level sd_llc can point to is MC. That will impact all callsites using cpus_share_cache(): in the eMAG case, only pairs of cores will be seen as sharing cache, even though *all* cores share the same L3.
I'm trying to paint a picture of what the P9 topology looks like (the one you showcase in your cover letter) to see if there are any similarities; from what I gather in [1], wikichips and your cover letter, with P9 you can have something like this in a single DIE (somewhat unsure about L3 setup; it looks to be distributed?)
+---------------------------------------------------------------------+ | L3 | +---------------+-+---------------+-+---------------+-+---------------+ | L2 | | L2 | | L2 | | L2 | +------+-+------+ +------+-+------+ +------+-+------+ +------+-+------+ | L1 | | L1 | | L1 | | L1 | | L1 | | L1 | | L1 | | L1 | +------+ +------+ +------+ +------+ +------+ +------+ +------+ +------+ |4 CPUs| |4 CPUs| |4 CPUs| |4 CPUs| |4 CPUs| |4 CPUs| |4 CPUs| |4 CPUs| +------+ +------+ +------+ +------+ +------+ +------+ +------+ +------+
Which would lead to (ignoring the whole SMT CPU numbering shenanigans)
NUMA [ ... DIE [ ] MC [ ] [ ] [ ] [ ] BIGCORE [ ] [ ] [ ] [ ] SMT [ ] [ ] [ ] [ ] [ ] [ ] [ ] [ ] 00-03 04-07 08-11 12-15 16-19 20-23 24-27 28-31 <other node here>
This however has MC == BIGCORE; what makes it you can have different spans for these two domains? If it's not too much to ask, I'd love to have a P9 topology diagram.
[1]: 20200722081822.GG9290@linux.vnet.ibm.com
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