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    Subject[PATCH v2 05/18] clk: at91: sam9x60-pll: check fcore against ranges
    Date
    According to datasheet the range of 600-1200MHz is for the
    frequency generated by the fractional part of the PLL (namely
    Fcorepllck according to datasheet). With this in mind the output
    range of the PLL itself (fractional + div), taking into account
    that the divider is 8 bits wide, is 600/256-1200Hz=2.3-1200MHz.

    Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
    Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
    ---
    drivers/clk/at91/clk-sam9x60-pll.c | 12 +++++++++++-
    drivers/clk/at91/sam9x60.c | 2 +-
    2 files changed, 12 insertions(+), 2 deletions(-)

    diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
    index 4b7b6c435d4e..a933abebfbaf 100644
    --- a/drivers/clk/at91/clk-sam9x60-pll.c
    +++ b/drivers/clk/at91/clk-sam9x60-pll.c
    @@ -21,6 +21,9 @@
    #define UPLL_DIV 2
    #define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)

    +#define FCORE_MIN (600000000)
    +#define FCORE_MAX (1200000000)
    +
    #define PLL_MAX_ID 1

    struct sam9x60_pll {
    @@ -168,6 +171,7 @@ static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll,
    unsigned long bestdiv = 0;
    unsigned long bestmul = 0;
    unsigned long bestfrac = 0;
    + u64 fcore = 0;

    if (rate < characteristics->output[0].min ||
    rate > characteristics->output[0].max)
    @@ -212,6 +216,11 @@ static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll,
    remainder = rate - tmprate;
    }

    + fcore = parent_rate * (tmpmul + 1) +
    + ((u64)parent_rate * tmpfrac >> 22);
    + if (fcore < FCORE_MIN || fcore > FCORE_MAX)
    + continue;
    +
    /*
    * Compare the remainder with the best remainder found until
    * now and elect a new best multiplier/divider pair if the
    @@ -231,7 +240,8 @@ static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll,
    }

    /* Check if bestrate is a valid output rate */
    - if (bestrate < characteristics->output[0].min ||
    + if (fcore < FCORE_MIN || fcore > FCORE_MAX ||
    + bestrate < characteristics->output[0].min ||
    bestrate > characteristics->output[0].max)
    return -ERANGE;

    diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
    index 3e20aa68259f..633891b98d43 100644
    --- a/drivers/clk/at91/sam9x60.c
    +++ b/drivers/clk/at91/sam9x60.c
    @@ -22,7 +22,7 @@ static const struct clk_master_layout sam9x60_master_layout = {
    };

    static const struct clk_range plla_outputs[] = {
    - { .min = 300000000, .max = 600000000 },
    + { .min = 2343750, .max = 1200000000 },
    };

    static const struct clk_pll_characteristics plla_characteristics = {
    --
    2.7.4
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