lkml.org 
[lkml]   [2020]   [Jul]   [20]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 5.7 144/244] clk: qcom: gcc: Add missing UFS clocks for SM8150
    Date
    From: Vinod Koul <vkoul@kernel.org>

    commit 37c72e4cae37f0dace1abb3711ede7fbc6d0862a upstream.

    Add the missing ufs card and ufs phy clocks for SM8150. They were missed
    in earlier addition of clock driver.

    Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150")
    Signed-off-by: Vinod Koul <vkoul@kernel.org>
    Link: https://lkml.kernel.org/r/20200513065420.32735-2-vkoul@kernel.org
    Signed-off-by: Stephen Boyd <sboyd@kernel.org>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/clk/qcom/gcc-sm8150.c | 84 ++++++++++++++++++++++++++++++++++++++++++
    1 file changed, 84 insertions(+)

    --- a/drivers/clk/qcom/gcc-sm8150.c
    +++ b/drivers/clk/qcom/gcc-sm8150.c
    @@ -2872,6 +2872,45 @@ static struct clk_branch gcc_ufs_card_ph
    },
    };

    +/* external clocks so add BRANCH_HALT_SKIP */
    +static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
    + .halt_check = BRANCH_HALT_SKIP,
    + .clkr = {
    + .enable_reg = 0x7501c,
    + .enable_mask = BIT(0),
    + .hw.init = &(struct clk_init_data){
    + .name = "gcc_ufs_card_rx_symbol_0_clk",
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    +/* external clocks so add BRANCH_HALT_SKIP */
    +static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
    + .halt_check = BRANCH_HALT_SKIP,
    + .clkr = {
    + .enable_reg = 0x750ac,
    + .enable_mask = BIT(0),
    + .hw.init = &(struct clk_init_data){
    + .name = "gcc_ufs_card_rx_symbol_1_clk",
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    +/* external clocks so add BRANCH_HALT_SKIP */
    +static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
    + .halt_check = BRANCH_HALT_SKIP,
    + .clkr = {
    + .enable_reg = 0x75018,
    + .enable_mask = BIT(0),
    + .hw.init = &(struct clk_init_data){
    + .name = "gcc_ufs_card_tx_symbol_0_clk",
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    static struct clk_branch gcc_ufs_card_unipro_core_clk = {
    .halt_reg = 0x75058,
    .halt_check = BRANCH_HALT,
    @@ -3052,6 +3091,45 @@ static struct clk_branch gcc_ufs_phy_phy
    },
    };

    +/* external clocks so add BRANCH_HALT_SKIP */
    +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
    + .halt_check = BRANCH_HALT_SKIP,
    + .clkr = {
    + .enable_reg = 0x7701c,
    + .enable_mask = BIT(0),
    + .hw.init = &(struct clk_init_data){
    + .name = "gcc_ufs_phy_rx_symbol_0_clk",
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    +/* external clocks so add BRANCH_HALT_SKIP */
    +static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
    + .halt_check = BRANCH_HALT_SKIP,
    + .clkr = {
    + .enable_reg = 0x770ac,
    + .enable_mask = BIT(0),
    + .hw.init = &(struct clk_init_data){
    + .name = "gcc_ufs_phy_rx_symbol_1_clk",
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    +/* external clocks so add BRANCH_HALT_SKIP */
    +static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
    + .halt_check = BRANCH_HALT_SKIP,
    + .clkr = {
    + .enable_reg = 0x77018,
    + .enable_mask = BIT(0),
    + .hw.init = &(struct clk_init_data){
    + .name = "gcc_ufs_phy_tx_symbol_0_clk",
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
    .halt_reg = 0x77058,
    .halt_check = BRANCH_HALT,
    @@ -3548,6 +3626,9 @@ static struct clk_regmap *gcc_sm8150_clo
    [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
    [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] =
    &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
    + [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
    + [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
    + [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
    [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
    [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
    &gcc_ufs_card_unipro_core_clk_src.clkr,
    @@ -3565,6 +3646,9 @@ static struct clk_regmap *gcc_sm8150_clo
    [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
    [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
    [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
    + [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
    + [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
    + [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
    [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
    [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
    &gcc_ufs_phy_unipro_core_clk_src.clkr,

    \
     
     \ /
      Last update: 2020-07-20 18:14    [W:4.045 / U:0.012 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site