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SubjectRe: [PATCH v12 00/11] Guest Last Branch Recording Enabling
On Sat, Jun 13, 2020 at 04:09:45PM +0800, Like Xu wrote:
> Like Xu (10):
> perf/x86/core: Refactor hw->idx checks and cleanup
> perf/x86/lbr: Add interface to get LBR information
> perf/x86: Add constraint to create guest LBR event without hw counter
> perf/x86: Keep LBR records unchanged in host context for guest usage

> Wei Wang (1):
> perf/x86: Fix variable types for LBR registers

> arch/x86/events/core.c | 26 +--
> arch/x86/events/intel/core.c | 109 ++++++++-----
> arch/x86/events/intel/lbr.c | 51 +++++-
> arch/x86/events/perf_event.h | 8 +-
> arch/x86/include/asm/perf_event.h | 34 +++-

These look good to me; but at the same time Kan is sending me
Architectural LBR patches.

Kan, if I take these perf patches and stick them in a tip/perf/vlbr
topic branch, can you rebase the arch lbr stuff on top, or is there
anything in the arch-lbr series that badly conflicts with this work?

Paolo, would that topic branch work for you too, to then stick these
patches in top?

> KVM: vmx/pmu: Expose LBR to guest via MSR_IA32_PERF_CAPABILITIES
> KVM: vmx/pmu: Unmask LBR fields in the MSR_IA32_DEBUGCTLMSR emualtion
> KVM: vmx/pmu: Pass-through LBR msrs when guest LBR event is scheduled
> KVM: vmx/pmu: Emulate legacy freezing LBRs on virtual PMI
> KVM: vmx/pmu: Reduce the overhead of LBR pass-through or cancellation
> KVM: vmx/pmu: Release guest LBR event via lazy release mechanism

> arch/x86/kvm/pmu.c | 12 +-
> arch/x86/kvm/pmu.h | 5 +
> arch/x86/kvm/vmx/capabilities.h | 23 ++-
> arch/x86/kvm/vmx/pmu_intel.c | 253 +++++++++++++++++++++++++++++-
> arch/x86/kvm/vmx/vmx.c | 86 +++++++++-
> arch/x86/kvm/vmx/vmx.h | 17 ++
> arch/x86/kvm/x86.c | 13 --

> 12 files changed, 559 insertions(+), 78 deletions(-)

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