Messages in this thread | | | From | Sven Van Asbroeck <> | Subject | [PATCH v1 0/5] imx6qp QuadPlus: support improved enet clocking | Date | Sun, 12 Jul 2020 20:25:07 -0400 |
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On the imx6qp QuadPlus, the h/w designers have improved enet clocking.
This patchset extends the clock tree to reflect the situation on QuadPlus.
This allows board designers to choose the enet clocking method by making simple clocktree changes in the devicetree.
Default setting: external routing of enet_ref from pad to pad.
Example, change the default to enet_ref @ 125MHz clock routed internally:
&fec { assigned-clocks = <&clks IMX6QDL_CLK_ENET_PTP>, <&clks IMX6QDL_CLK_ENET_REF>; assigned-clock-parents = <&clks IMX6QDL_CLK_ENET_REF>; assigned-clock-rates = <0>, <125000000>; };
To: Shawn Guo <shawnguo@kernel.org> To: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org
Sven Van Asbroeck (5): ARM: mach-imx6q: do not select enet PTP clock source on QuadPlus clk: imx: add simple regmap-backed clock mux dt-bindings: imx6qdl-clock: add QuadPlus enet clocks clk: imx6q: support improved enet clocking on QuadPlus ARM: dts: imx6qp: support improved enet clocking on QuadPlus
.../bindings/clock/imx6q-clock.yaml | 2 + arch/arm/boot/dts/imx6qp.dtsi | 3 + arch/arm/mach-imx/mach-imx6q.c | 4 + drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-imx6q.c | 46 ++++++++ drivers/clk/imx/clk-mux-regmap.c | 110 ++++++++++++++++++ drivers/clk/imx/clk.h | 7 ++ include/dt-bindings/clock/imx6qdl-clock.h | 5 +- include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + 9 files changed, 178 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/imx/clk-mux-regmap.c
-- 2.17.1
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