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    Subject[PATCH 17/21] iommu/mediatek: Support report iova 34bit translation fault in ISR
    Date
    If the iova is over 32bit, the fault status register bit is a little
    different. Add a flag for the special register bits.

    Signed-off-by: Yong Wu <yong.wu@mediatek.com>
    ---
    drivers/iommu/mtk_iommu.c | 18 ++++++++++++++++--
    1 file changed, 16 insertions(+), 2 deletions(-)

    diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
    index 9c6649a97bd7..766c9e73d541 100644
    --- a/drivers/iommu/mtk_iommu.c
    +++ b/drivers/iommu/mtk_iommu.c
    @@ -4,6 +4,7 @@
    * Author: Yong Wu <yong.wu@mediatek.com>
    */
    #include <linux/memblock.h>
    +#include <linux/bitfield.h>
    #include <linux/bug.h>
    #include <linux/clk.h>
    #include <linux/component.h>
    @@ -87,6 +88,9 @@
    #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7)

    #define REG_MMU0_FAULT_VA 0x13c
    +#define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12)
    +#define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9)
    +#define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6)
    #define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
    #define F_MMU_FAULT_VA_LAYER_BIT BIT(0)

    @@ -110,6 +114,7 @@
    #define OUT_ORDER_WR_EN BIT(4)
    #define HAS_SUB_COMM BIT(5)
    #define WR_THROT_EN BIT(6)
    +#define IOVA_34_EN BIT(7)

    #define MTK_IOMMU_HAS_FLAG(pdata, _x) \
    ((((pdata)->flags) & (_x)) == (_x))
    @@ -269,8 +274,9 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
    {
    struct mtk_iommu_data *data = dev_id;
    struct mtk_iommu_domain *dom = data->m4u_dom;
    - u32 int_state, regval, fault_iova, fault_pa;
    unsigned int fault_larb, fault_port, sub_comm = 0;
    + u32 int_state, regval, va34_32, pa34_32;
    + u64 fault_iova, fault_pa;
    bool layer, write;

    /* Read error info from registers */
    @@ -286,6 +292,14 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
    }
    layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
    write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
    + if (MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN)) {
    + va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova);
    + pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
    + fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK;
    + fault_iova |= (u64)va34_32 << 32;
    + fault_pa |= (u64)pa34_32 << 32;
    + }
    +
    fault_port = F_MMU_INT_ID_PORT_ID(regval);
    if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) {
    fault_larb = F_MMU_INT_ID_COMM_ID(regval);
    @@ -299,7 +313,7 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
    write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
    dev_err_ratelimited(
    data->dev,
    - "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n",
    + "fault type=0x%x iova=0x%llx pa=0x%llx larb=%d port=%d layer=%d %s\n",
    int_state, fault_iova, fault_pa, fault_larb, fault_port,
    layer, write ? "write" : "read");
    }
    --
    2.18.0
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