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    SubjectRe: [PATCH v7 6/7] clk: mediatek: add UART0 clock support
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    On 02/07/2020 14:57, Hanks Chen wrote:
    > Add MT6779 UART0 clock support.
    >
    > Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
    > Signed-off-by: Wendell Lin <wendell.lin@mediatek.com>
    > Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>

    Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>

    > ---
    > drivers/clk/mediatek/clk-mt6779.c | 2 ++
    > 1 file changed, 2 insertions(+)
    >
    > diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
    > index 9766ccc..6e0d3a1 100644
    > --- a/drivers/clk/mediatek/clk-mt6779.c
    > +++ b/drivers/clk/mediatek/clk-mt6779.c
    > @@ -919,6 +919,8 @@
    > "pwm_sel", 19),
    > GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
    > "pwm_sel", 21),
    > + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
    > + "uart_sel", 22),
    > GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
    > "uart_sel", 23),
    > GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
    >

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