Messages in this thread | | | Date | Wed, 03 Jun 2020 17:42:28 +0800 | From | "李扬韬" <> | Subject | 回复:[PATCH 1/4] clk: sunxi-ng: add support for th e Allwinner A100 CCU |
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>> + /* Enable the lock bits on all PLLs */ >> + for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { >> + val = readl(reg + pll_regs[i]); >> + val |= BIT(29); > >Having a define for that would be nice here > >> + writel(val, reg + pll_regs[i]); >> + } >> + >> + /* >> + * In order to pass the EMI certification, the SDM function of >> + * the peripheral 1 bus is enabled, and the frequency is still >> + * calculated using the previous division factor. >> + */ >> + writel(0xd1303333, reg + SUN50I_A100_PLL_PERIPH1_PATTERN0_REG); > >Same here
Having a define? I don’t quite understand what you mean, can you give me an example?
MBR, Yangtao | |