lkml.org 
[lkml]   [2020]   [Jun]   [29]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
Subject[PATCHv3 0/7] System Cache support for GPU and required SMMU support
Date
Some hardware variants contain a system cache or the last level
cache(llc). This cache is typically a large block which is shared
by multiple clients on the SOC. GPU uses the system cache to cache
both the GPU data buffers(like textures) as well the SMMU pagetables.
This helps with improved render performance as well as lower power
consumption by reducing the bus traffic to the system memory.

The system cache architecture allows the cache to be split into slices
which then be used by multiple SOC clients. This patch series is an
effort to enable and use two of those slices perallocated for the GPU,
one for the GPU data buffers and another for the GPU SMMU hardware
pagetables.

Patch 1 adds a init_context_bank implementation hook to set SCTLR.HUPCF.
Patch 2,3,6,7 adds system cache support in SMMU and GPU driver.
Patch 4 and 5 are minor cleanups for arm-smmu impl.

Changes in v3:
* Fix domain attribute setting to before iommu_attach_device()
* Fix few code style and checkpatch warnings
* Rebase on top of Jordan's latest split pagetables and per-instance
pagetables support [1][2]

Changes in v2:
* Addressed review comments and rebased on top of Jordan's split
pagetables series

[1] https://lore.kernel.org/patchwork/cover/1264446/
[2] https://lore.kernel.org/patchwork/cover/1264460/

Jordan Crouse (1):
iommu/arm-smmu: Add a init_context_bank implementation hook

Sai Prakash Ranjan (4):
iommu/io-pgtable-arm: Add support to use system cache
iommu/arm-smmu: Add domain attribute for system cache
iommu: arm-smmu-impl: Remove unwanted extra blank lines
iommu: arm-smmu-impl: Convert to use of_match_node() for qcom impl

Sharat Masetty (2):
drm/msm: rearrange the gpu_rmw() function
drm/msm/a6xx: Add support for using system cache(LLC)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 82 +++++++++++++++++++++++++
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 3 +
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 23 ++++++-
drivers/gpu/drm/msm/msm_drv.c | 8 +++
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gpu.h | 5 +-
drivers/gpu/drm/msm/msm_iommu.c | 3 +
drivers/gpu/drm/msm/msm_mmu.h | 4 ++
drivers/iommu/arm-smmu-impl.c | 13 ++--
drivers/iommu/arm-smmu-qcom.c | 13 ++++
drivers/iommu/arm-smmu.c | 46 +++++++++-----
drivers/iommu/arm-smmu.h | 13 ++++
drivers/iommu/io-pgtable-arm.c | 7 ++-
include/linux/io-pgtable.h | 4 ++
include/linux/iommu.h | 1 +
15 files changed, 198 insertions(+), 28 deletions(-)

--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

\
 
 \ /
  Last update: 2020-06-29 23:36    [W:0.078 / U:3.292 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site