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SubjectRe: [PATCH v4 02/10] dmaengine: Actions: Add support for S700 DMA engine
On 24-06-20, 10:35, André Przywara wrote:
> On 24/06/2020 07:15, Vinod Koul wrote:
> > On 09-06-20, 15:47, Amit Singh Tomar wrote:
> >
> >> @@ -372,6 +383,7 @@ static inline int owl_dma_cfg_lli(struct owl_dma_vchan *vchan,
> >> struct dma_slave_config *sconfig,
> >> bool is_cyclic)
> >> {
> >> + struct owl_dma *od = to_owl_dma(vchan->vc.chan.device);
> >> u32 mode, ctrlb;
> >>
> >> mode = OWL_DMA_MODE_PW(0);
> >> @@ -427,14 +439,26 @@ static inline int owl_dma_cfg_lli(struct owl_dma_vchan *vchan,
> >> lli->hw[OWL_DMADESC_DADDR] = dst;
> >> lli->hw[OWL_DMADESC_SRC_STRIDE] = 0;
> >> lli->hw[OWL_DMADESC_DST_STRIDE] = 0;
> >> - /*
> >> - * Word starts from offset 0xC is shared between frame length
> >> - * (max frame length is 1MB) and frame count, where first 20
> >> - * bits are for frame length and rest of 12 bits are for frame
> >> - * count.
> >> - */
> >> - lli->hw[OWL_DMADESC_FLEN] = len | FCNT_VAL << 20;
> >> - lli->hw[OWL_DMADESC_CTRLB] = ctrlb;
> >> +
> >> + if (od->devid == S700_DMA) {
> >> + /* Max frame length is 1MB */
> >> + lli->hw[OWL_DMADESC_FLEN] = len;
> >> + /*
> >> + * On S700, word starts from offset 0x1C is shared between
> >> + * frame count and ctrlb, where first 12 bits are for frame
> >> + * count and rest of 20 bits are for ctrlb.
> >> + */
> >> + lli->hw[OWL_DMADESC_CTRLB] = FCNT_VAL | ctrlb;
> >> + } else {
> >> + /*
> >> + * On S900, word starts from offset 0xC is shared between
> >> + * frame length (max frame length is 1MB) and frame count,
> >> + * where first 20 bits are for frame length and rest of
> >> + * 12 bits are for frame count.
> >> + */
> >> + lli->hw[OWL_DMADESC_FLEN] = len | FCNT_VAL << 20;
> >> + lli->hw[OWL_DMADESC_CTRLB] = ctrlb;
> >
> > Unfortunately this wont scale, we will keep adding new conditions for
> > newer SoC's! So rather than this why not encode max frame length in
> > driver_data rather than S900_DMA/S700_DMA.. In future one can add values
> > for newer SoC and not code above logic again.
>
> What newer SoCs? I don't think we should try to guess the future here.

In a patch for adding new SoC, quite ironical I would say!

> We can always introduce further abstractions later, once we actually
> *know* what we are looking at.

Rather if we know we are adding abstractions, why not add in a way that
makes it scale better rather than rework again

> Besides, I don't understand what you are after. The max frame length is
> 1MB in both cases, it's just a matter of where to put FCNT_VAL, either
> in FLEN or in CTRLB. And having an extra flag for that in driver data
> sounds a bit over the top at the moment.

Maybe, maybe not. I would rather make it support N SoC when adding
support for second one rather than keep adding everytime a new SoC is
added...

--
~Vinod

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