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    Subject[PATCH v4 1/8] dt-bindings: add documentation of xilinx clocking wizard
    Date
    Add the devicetree binding for the xilinx clocking wizard.

    Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
    ---
    v4:
    Move to yaml format

    .../bindings/clock/xlnx,clocking-wizard.yaml | 71 ++++++++++++++++++++++
    1 file changed, 71 insertions(+)
    create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml

    diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
    new file mode 100644
    index 0000000..5a8e991
    --- /dev/null
    +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
    @@ -0,0 +1,71 @@
    +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    +%YAML 1.2
    +---
    +$id: http://devicetree.org/schemas/clock/xlnx,clocking-wiz.yaml#
    +$schema: http://devicetree.org/meta-schemas/core.yaml#
    +
    +title: Xilinx clocking wizard
    +
    +maintainers:
    + - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
    +
    +description: |
    + The clocking wizard is a soft ip clocking block of Xilinx versal. It
    + reads required input clock frequencies from the devicetree and acts as clock
    + clock output.
    +
    +select: false
    +
    +properties:
    + compatible:
    + items:
    + - enum:
    + - xlnx,clocking-wizard
    + - xlnx,clocking-wizard-6.0
    +
    + "#clock-cells":
    + const: 1
    +
    + clocks:
    + description: List of clock specifiers which are external input
    + clocks to the given clock controller.
    + items:
    + - description: clock input
    + - description: axi clock
    +
    + clock-names:
    + items:
    + - const: clk_in1
    + - const: s_axi_aclk
    +
    + speed-grade:
    + allOf:
    + - $ref: /schemas/types.yaml#/definitions/uint32
    + - enum: [1, 2, 3]
    + description:
    + Speed grade of the device.
    + maxItems: 1
    +
    +required:
    + - compatible
    + - "#clock-cells"
    + - clocks
    + - clock-names
    + - speed-grade
    +
    +additionalProperties: false
    +
    +examples:
    + - |
    + clock-generator@40040000 {
    + #clock-cells = <1>;
    + reg = <0x40040000 0x1000>;
    + compatible = "xlnx,clk-wizard-1.0";
    + speed-grade = <1>;
    + clock-names = "clk_in1", "s_axi_aclk";
    + clocks = <&clkc 15>, <&clkc 15>;
    + clock-output-names = "clk_out1", "clk_out2",
    + "clk_out3", "clk_out4", "clk_out5",
    + "clk_out6", "clk_out7";
    + };
    +...
    --
    2.1.1
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