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    Subject[PATCH 5.7 030/477] PCI: brcmstb: Fix window register offset from 4 to 8
    Date
    From: Jim Quinlan <jquinlan@broadcom.com>

    [ Upstream commit 077a4fa92a615a4d0f86eae68d777b9dd5e5a95b ]

    The outbound memory window registers were being referenced
    with an incorrect stride offset. This probably wasn't noticed
    previously as there was likely only one such window employed.

    Link: https://lore.kernel.org/r/20200507201544.43432-3-james.quinlan@broadcom.com
    Fixes: c0452137034b ("PCI: brcmstb: Add Broadcom STB PCIe host controller driver")
    Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Acked-by: Florian Fainelli <f.fainelli@gmail.com>
    Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/pci/controller/pcie-brcmstb.c | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
    index 6d79d14527a66..c9ecc4d639c19 100644
    --- a/drivers/pci/controller/pcie-brcmstb.c
    +++ b/drivers/pci/controller/pcie-brcmstb.c
    @@ -54,11 +54,11 @@

    #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
    #define PCIE_MEM_WIN0_LO(win) \
    - PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
    + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8)

    #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
    #define PCIE_MEM_WIN0_HI(win) \
    - PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
    + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8)

    #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
    #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
    --
    2.25.1


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