lkml.org 
[lkml]   [2020]   [Jun]   [2]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    Date
    From
    SubjectRe: [PATCH v3 70/75] x86/head/64: Setup TSS early for secondary CPUs
    On Tue, Apr 28, 2020 at 05:17:20PM +0200, Joerg Roedel wrote:
    > From: Joerg Roedel <jroedel@suse.de>
    >
    > The #VC exception will trigger very early in head_64.S, when the first
    > CPUID instruction is executed. When secondary CPUs boot, they already
    > load the real system IDT, which has the #VC handler configured to be
    > using an IST stack. IST stacks require a TSS to be loaded, to set up the
    > TSS early for bringing up the secondary CPUs. Use the RW version of
    > early, until cpu_init() switches to the RO mapping.

    I think you wanna say "Use the read-write version of the per-CPU TSS struct
    early." here.

    --
    Regards/Gruss,
    Boris.

    https://people.kernel.org/tglx/notes-about-netiquette

    \
     
     \ /
      Last update: 2020-06-02 17:47    [W:2.221 / U:0.432 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site