Messages in this thread | | | Date | Mon, 1 Jun 2020 12:06:47 -0300 | From | Arnaldo Carvalho de Melo <> | Subject | Re: [PATCH v8 2/3] perf auxtrace: Add four itrace options |
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Em Mon, Jun 01, 2020 at 10:24:00AM +0300, Adrian Hunter escreveu: > On 30/05/20 3:24 pm, Leo Yan wrote: > > From: Tan Xiaojun <tanxiaojun@huawei.com> > > > > This patch is to add four options to synthesize events which are > > described as below: > > > > 'f': synthesize first level cache events > > 'm': synthesize last level cache events > > 't': synthesize TLB events > > 'a': synthesize remote access events > > > > This four options will be used by ARM SPE as their first consumer. > > > > Signed-off-by: Tan Xiaojun <tanxiaojun@huawei.com> > > Signed-off-by: James Clark <james.clark@arm.com> > > Signed-off-by: Leo Yan <leo.yan@linaro.org> > > Tested-by: James Clark <james.clark@arm.com> > > Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Thanks a lot!
- Arnaldo
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