Messages in this thread | | | Date | Mon, 4 May 2020 21:33:14 +0100 | From | Will Deacon <> | Subject | Re: [PATCH V3 06/16] arm64/cpufeature: Introduce ID_MMFR5 CPU register |
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On Sat, May 02, 2020 at 07:03:55PM +0530, Anshuman Khandual wrote: > This adds basic building blocks required for ID_MMFR5 CPU register which > provides information about the implemented memory model and memory > management support in AArch32 state. This is added per ARM DDI 0487F.a > specification. > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Marc Zyngier <maz@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: James Morse <james.morse@arm.com> > Cc: Suzuki K Poulose <suzuki.poulose@arm.com> > Cc: kvmarm@lists.cs.columbia.edu > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > > Suggested-by: Will Deacon <will@kernel.org> > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> > --- > arch/arm64/include/asm/cpu.h | 1 + > arch/arm64/include/asm/sysreg.h | 3 +++ > arch/arm64/kernel/cpufeature.c | 10 ++++++++++ > arch/arm64/kernel/cpuinfo.c | 1 + > arch/arm64/kvm/sys_regs.c | 2 +- > 5 files changed, 16 insertions(+), 1 deletion(-)
[...]
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 2ce952d9668d..c790cc200bb1 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -403,6 +403,11 @@ static const struct arm64_ftr_bits ftr_id_isar4[] = { > ARM64_FTR_END, > }; > > +static const struct arm64_ftr_bits ftr_id_mmfr5[] = { > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0), > + ARM64_FTR_END, > +}; > + > static const struct arm64_ftr_bits ftr_id_isar6[] = { > ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0), > @@ -527,6 +532,7 @@ static const struct __ftr_reg_entry { > ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), > ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), > ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), > + ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), > > /* Op1 = 0, CRn = 0, CRm = 4 */ > ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), > @@ -732,6 +738,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) > init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); > init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); > init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); > + init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); > init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); > init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); > init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); > @@ -866,6 +873,8 @@ static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info, > info->reg_id_mmfr2, boot->reg_id_mmfr2); > taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, > info->reg_id_mmfr3, boot->reg_id_mmfr3);
Looks like MMFR4 is missing here?
> + taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, > + info->reg_id_mmfr5, boot->reg_id_mmfr5);
Will
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