Re: [PATCH 1/3] CLK: HSDK: CGU: check if PLL is bypassed first
From
Stephen Boyd <>
Date
Thu, 28 May 2020 21:07:23 -0700
Quoting Eugeniy Paltsev (2020-03-11 06:41:13) > If PLL is bypassed the EN (enable) bit has no effect on > output clock. > > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> > ---