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SubjectHigh interrupt latency with low power idle mode on i.MX6
Date
Hi,

on our i.MX6UL/ULL boards running mainline kernels, we see an issue with
RS485 collisions on the bus. These are caused by the resetting of the
RTS signal being delayed after each transmission. The TXDC interrupt
takes several milliseconds to trigger and the slave on the bus already
starts to send a reply in the meantime.

We found out that these delays only happen when the CPU is in "low power
idle" mode (ARM power off). When we disable cpuidle state 2 or put some
background load on the CPU everything works fine and the delays are gone.

echo 1 > /sys/devices/system/cpu/cpu0/cpuidle/state2/disable

It seems like also other interfaces (I2C, etc.) might be affected by
these increased latencies, we haven't investigated this more closely,
though.

We currently apply a patch to our kernel, that disables low power idle
mode by default, but I'm wondering if there's a way to fix this
properly? Any ideas?

Thanks,
Frieder
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