| Date | Mon, 25 May 2020 11:53:46 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH v3 53/75] x86/sev-es: Handle MSR events |
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On Tue, Apr 28, 2020 at 05:17:03PM +0200, Joerg Roedel wrote: > From: Tom Lendacky <thomas.lendacky@amd.com> > > Implement a handler for #VC exceptions caused by RDMSR/WRMSR > instructions. > > Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> > [ jroedel@suse.de: Adapt to #VC handling infrastructure ] > Co-developed-by: Joerg Roedel <jroedel@suse.de> > Signed-off-by: Joerg Roedel <jroedel@suse.de> > --- > arch/x86/kernel/sev-es.c | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/arch/x86/kernel/sev-es.c b/arch/x86/kernel/sev-es.c > index 84958a82f8e0..e43bba4c7d79 100644 > --- a/arch/x86/kernel/sev-es.c > +++ b/arch/x86/kernel/sev-es.c > @@ -316,6 +316,31 @@ static phys_addr_t vc_slow_virt_to_phys(struct ghcb *ghcb, unsigned long vaddr) > /* Include code shared with pre-decompression boot stage */ > #include "sev-es-shared.c" > > +static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt) > +{ > + struct pt_regs *regs = ctxt->regs; > + enum es_result ret; > + u64 exit_info_1; > +
A comment pls:
/* Is it a WRMSR? */
> + exit_info_1 = (ctxt->insn.opcode.bytes[1] == 0x30) ? 1 : 0; > + > + ghcb_set_rcx(ghcb, regs->cx); > + if (exit_info_1) { > + ghcb_set_rax(ghcb, regs->ax); > + ghcb_set_rdx(ghcb, regs->dx); > + exit_info_1 = 1;
No need to set it again - you just did above. :)
-- Regards/Gruss, Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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