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SubjectRe: [PATCH 2/3] drm/etnaviv: Don't ignore errors on getting clocks
Cc += robh

On Wed, May 20, 2020 at 04:04:39PM +0200, Lucas Stach wrote:
> Am Mittwoch, den 20.05.2020, 15:38 +0200 schrieb Lubomir Rintel:
> > On Thu, May 14, 2020 at 09:53:08AM +0100, Russell King - ARM Linux admin wrote:
> > > On Thu, May 14, 2020 at 10:40:58AM +0200, Lucas Stach wrote:
> > > > Am Donnerstag, den 14.05.2020, 09:27 +0100 schrieb Russell King - ARM Linux admin:
> > > > > On Thu, May 14, 2020 at 10:18:02AM +0200, Lucas Stach wrote:
> > > > > > Am Mittwoch, den 13.05.2020, 23:41 -0300 schrieb Fabio Estevam:
> > > > > > > On Wed, May 13, 2020 at 2:09 PM Fabio Estevam <festevam@gmail.com> wrote:
> > > > > > >
> > > > > > > > The binding doc Documentation/devicetree/bindings/gpu/vivante,gc.yaml
> > > > > > > > says that only the 'reg' clock could be optional, the others are
> > > > > > > > required.
> > > > > > >
> > > > > > > arch/arm/boot/dts/dove.dtsi only uses the 'core' clock.
> > > > > > > arch/arm/boot/dts/stm32mp157.dtsi uses 'bus' and 'core'
> > > > > > >
> > > > > > > Maybe the binding needs to be updated and it seems that using
> > > > > > > devm_clk_get_optional() like you propose is safe.
> > > > > >
> > > > > > The binding is correct as-is. We want to require those clocks to be
> > > > > > present, but the dove DT was added before the binding was finalized, so
> > > > > > the driver still treats the clocks as optional to not break
> > > > > > compatibility with old DTs. Maybe this warrants a comment in the
> > > > > > code...
> > > > >
> > > > > The binding doc in mainline says:
> > > > >
> > > > > clocks:
> > > > > items:
> > > > > - description: AXI/master interface clock
> > > > > - description: GPU core clock
> > > > > - description: Shader clock (only required if GPU has feature PIPE_3D)
> > > > > - description: AHB/slave interface clock (only required if GPU can gate slave interface independently)
> > > > > minItems: 1
> > > > > maxItems: 4
> > > > >
> > > > > clock-names:
> > > > > items:
> > > > > enum: [ bus, core, shader, reg ]
> > > > > minItems: 1
> > > > > maxItems: 4
> > > > >
> > > > > which looks correct to me - and means that Dove is compliant with that.
> > > >
> > > > The YAML binding actually did loose something in translation here,
> > > > which I didn't notice. Previously all those clocks were listed under
> > > > "Required properties", with the exceptions listed in parenthesis. So
> > > > the Dove GPU, which is a combined 2D/3D core should have axi, core and
> > > > shader clocks specified.
> > >
> > > That may be your desire, but that is impossible without knowing that
> > > (a) it has the clocks
> > > (b) what those clocks are connected to
> > >
> > > I guess we could "make something up" but as DT is supposed to describe
> > > hardware, I don't see how we can satisfy that and your requirement.
> > >
> > > The only thing that is known from the documentation is that there is
> > > one clock for the GPU on Dove.
> >
> > Yes. This means that in fact "core" is the only required clock for all
> > implementations of vivante,gc and the common binding needs to be updated
> > to reflect that. I'll follow with a patch that does that, unless there
> > are strong objections.
> >
> > If there are implementations that require different clock inputs, then they
> > need to use additional compatible string for the particular flavor and the
> > binding should have conditionals for them. Something like this:
> >
> > if:
> > properties:
> > compatible:
> > contains:
> > const: fsl,imx6sx-gpu
> > then:
> > properties:
> > clocks:
> > minItems: 4
>
> The DT binding of a device should describe the hardware of the device,
> not the specific integration into a SoC.

I'm not too convinced about this. While I'm not able to produce a
reference from a quick view either into ieee1275 and DTSpec, I believe
the DT describes the hardware from software's perspective.

That is, there's no point in describing hardware implementation details
that have no bearing on software interface (such as a single
software-controlled clock being routed to different parts of a chip).

Adding Rob to Cc, he will likely be able to clarify.

> Now it's a bit hard to make
> any definite statements about the Vivante GC GPU module itself, as most
> of the information we have is from reverse engineering. It's pretty
> clear though that the GPU module has at least 2 clock inputs: axi and
> core, as there is a feature bit that tells us if it's okay to gate the
> axi clock independently from core.
>
> I'm not 100% sure about the older cores as found in Dove, but all the
> more recent cores allow to clock the shader partition independently of
> the core partition, so that's another clock input.
>
> Now when it comes to a SoC integration, it's totally fine to have all
> those GPU module clock inputs fed from the same clock source and behind
> a shared gate maybe. But that doesn't change the clock inputs from the
> device perspective, it's still 3 independent clock inputs, which then
> just point to the same clock source in the DT.
>
> imx6sx.dtsi is even a precedent of such a setup: all module clock
> inputs are fed by a common clock and share a single gate.
>
> Regards,
> Lucas

Lubo

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