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    Subject[PATCH 5.4 045/147] drm/amd/display: check if REFCLK_CNTL register is present
    Date
    From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

    [ Upstream commit 3159d41db3a04330c31ece32f8b29752fc114848 ]

    Check before programming the register since it isn't present on
    all IPs using this code.

    Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
    Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
    Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 ++-
    1 file changed, 2 insertions(+), 1 deletion(-)

    diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
    index e933f6a369f92..083c42e521f5c 100644
    --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
    +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
    @@ -2015,7 +2015,8 @@ static void dcn20_fpga_init_hw(struct dc *dc)

    REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
    REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
    - REG_WRITE(REFCLK_CNTL, 0);
    + if (REG(REFCLK_CNTL))
    + REG_WRITE(REFCLK_CNTL, 0);
    //


    --
    2.20.1


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