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Subject[PATCH 13/14] arm64: dts: sparx5: Add Sparx5 SoC DPLL clock
Date
This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock
to misc peripherals, specifically the SDHCI/eMMC controller.

Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 45a60993789c8..ca4055f04ac26 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -82,6 +82,11 @@ sys_clk: sys-clk {
#clock-cells = <0>;
clock-frequency = <625000000>;
};
+ clks: clks@61110000c {
+ compatible = "microchip,sparx5-dpll";
+ #clock-cells = <1>;
+ reg = <0x6 0x1110000c 0x24>;
+ };
};

axi: axi@600000000 {
--
2.26.2
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