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SubjectRe: [PATCH v6 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC
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Hi Andy,
On 13/5/2020 11:34 pm, Andy Shevchenko wrote:
> On Wed, May 13, 2020 at 06:46:15PM +0800, Ramuthevar,Vadivel MuruganX wrote:
>> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>>
>> This patch adds the new IP of Nand Flash Controller(NFC) support
>> on Intel's Lightning Mountain(LGM) SoC.
>>
>> DMA is used for burst data transfer operation, also DMA HW supports
>> aligned 32bit memory address and aligned data access by default.
>> DMA burst of 8 supported. Data register used to support the read/write
>> operation from/to device.
>>
>> NAND controller driver implements ->exec_op() to replace legacy hooks,
>> these specific call-back method to execute NAND operations.
>
> ...
>
>> +static int ebu_nand_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct ebu_nand_controller *ebu_host;
>> + struct nand_chip *nand;
>> + struct mtd_info *mtd;
>> + struct resource *res;
>> + char *resname;
>> + int ret, i;
>> + u32 reg;
>> +
>> + ebu_host = devm_kzalloc(dev, sizeof(*ebu_host), GFP_KERNEL);
>> + if (!ebu_host)
>> + return -ENOMEM;
>> +
>> + ebu_host->dev = dev;
>> + nand_controller_init(&ebu_host->controller);
>> +
>> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ebunand");
>> + ebu_host->ebu = devm_ioremap_resource(&pdev->dev, res);
>
> devm_platform_ioremap_resource_byname
>
>> + if (IS_ERR(ebu_host->ebu))
>> + return PTR_ERR(ebu_host->ebu);
>> +
>> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsnand");
>> + ebu_host->hsnand = devm_ioremap_resource(&pdev->dev, res);
>
> devm_platform_ioremap_resource_byname
Thanks for the review comments
As Boris suggested , split into 2 API's.

>
>> + if (IS_ERR(ebu_host->hsnand))
>> + return PTR_ERR(ebu_host->hsnand);
>> +
>> + ret = device_property_read_u32(dev, "nand,cs", &reg);
>> + if (ret) {
>> + dev_err(dev, "failed to get chip select: %d\n", ret);
>> + return ret;
>> + }
>> + ebu_host->cs_num = reg;
>> +
>> + for (i = 0; i < MAX_CS; i++) {
>> + resname = devm_kasprintf(dev, GFP_KERNEL, "nand_cs%d", i);
>> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
>> + resname);
>
> if res is NULL?
Noted.
>
>> + ebu_host->cs[i].chipaddr = devm_ioremap_resource(dev, res);
>> + ebu_host->cs[i].nand_pa = res->start;
>> + if (IS_ERR(ebu_host->cs[i].chipaddr))
>> + return PTR_ERR(ebu_host->cs[i].chipaddr);
>
> Something happened with ordering / indentation along these lines...
Noted.
>
>> + }
>> +
>
>> + for (i = 0; i < MAX_CS; i++) {
>> + resname = devm_kasprintf(dev, GFP_KERNEL, "addr_sel%d", i);
>> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
>> + resname);
>
> if res is NULL?
Noted.

Regards
Vadivel
>
>> + ebu_host->cs[i].addr_sel = res->start;
>> + writel(ebu_host->cs[i].addr_sel | EBU_ADDR_MASK(5) |
>> + EBU_ADDR_SEL_REGEN, ebu_host->ebu + EBU_ADDR_SEL(i));
>> + }
>
>> + return ret;
>> +}
>
> ...
>
>> +static int ebu_nand_remove(struct platform_device *pdev)
>> +{
>> + struct ebu_nand_controller *ebu_host = platform_get_drvdata(pdev);
>> +
>
>> + if (ebu_host) {
>
> How it can be NULL here?
>
>> + mtd_device_unregister(nand_to_mtd(&ebu_host->chip));
>> + nand_cleanup(&ebu_host->chip);
>> + ebu_nand_disable(&ebu_host->chip);
>> +
>> + if (ebu_host->dma_rx || ebu_host->dma_tx)
>> + ebu_dma_cleanup(ebu_host);
>> +
>> + clk_disable_unprepare(ebu_host->clk);
>> + }
>> +
>> + return 0;
>> +}
>
>

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