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    Subject[PATCH 11/18] ARM: dts: r8a7742: Add SYS-DMAC support
    Date
    Describe SYS-DMAC0/1 in the R8A7742 device tree.

    Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
    Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
    ---
    arch/arm/boot/dts/r8a7742.dtsi | 66 ++++++++++++++++++++++++++++++++++++++++++
    1 file changed, 66 insertions(+)

    diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
    index 4c7baf2..0febd74 100644
    --- a/arch/arm/boot/dts/r8a7742.dtsi
    +++ b/arch/arm/boot/dts/r8a7742.dtsi
    @@ -448,6 +448,72 @@
    /* placeholder */
    };

    + dmac0: dma-controller@e6700000 {
    + compatible = "renesas,dmac-r8a7742",
    + "renesas,rcar-dmac";
    + reg = <0 0xe6700000 0 0x20000>;
    + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-names = "error",
    + "ch0", "ch1", "ch2", "ch3",
    + "ch4", "ch5", "ch6", "ch7",
    + "ch8", "ch9", "ch10", "ch11",
    + "ch12", "ch13", "ch14";
    + clocks = <&cpg CPG_MOD 219>;
    + clock-names = "fck";
    + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
    + resets = <&cpg 219>;
    + #dma-cells = <1>;
    + dma-channels = <15>;
    + };
    +
    + dmac1: dma-controller@e6720000 {
    + compatible = "renesas,dmac-r8a7742",
    + "renesas,rcar-dmac";
    + reg = <0 0xe6720000 0 0x20000>;
    + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-names = "error",
    + "ch0", "ch1", "ch2", "ch3",
    + "ch4", "ch5", "ch6", "ch7",
    + "ch8", "ch9", "ch10", "ch11",
    + "ch12", "ch13", "ch14";
    + clocks = <&cpg CPG_MOD 218>;
    + clock-names = "fck";
    + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
    + resets = <&cpg 218>;
    + #dma-cells = <1>;
    + dma-channels = <15>;
    + };
    +
    avb: ethernet@e6800000 {
    reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
    #address-cells = <1>;
    --
    2.7.4
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