Messages in this thread | | | Subject | Re: [PATCH v3 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC | From | "Ramuthevar, Vadivel MuruganX" <> | Date | Tue, 28 Apr 2020 14:17:30 +0800 |
| |
Hi Miquel,
Thank you very much for the review comments and your time...
On 27/4/2020 11:51 pm, Miquel Raynal wrote: > Hi Ramuthevar, > >>> +static int ebu_nand_probe(struct platform_device *pdev) >>> +{ >>> + struct device *dev = &pdev->dev; >>> + struct ebu_nand_controller *ebu_host; >>> + struct nand_chip *nand; >>> + phys_addr_t nandaddr_pa; >>> + struct mtd_info *mtd; >>> + struct resource *res; >>> + int ret; >>> + u32 cs; >>> + >>> + ebu_host = devm_kzalloc(dev, sizeof(*ebu_host), GFP_KERNEL); >>> + if (!ebu_host) >>> + return -ENOMEM; >>> + >>> + ebu_host->dev = dev; >>> + nand_controller_init(&ebu_host->controller); >>> + >>> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ebunand"); >>> + ebu_host->ebu_addr = devm_ioremap_resource(&pdev->dev, res); >>> + if (IS_ERR(ebu_host->ebu_addr)) >>> + return PTR_ERR(ebu_host->ebu_addr); >>> + >>> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsnand"); >>> + ebu_host->nand_addr = devm_ioremap_resource(&pdev->dev, res); >>> + if (IS_ERR(ebu_host->nand_addr)) >>> + return PTR_ERR(ebu_host->nand_addr); >>> + >>> + ret = device_property_read_u32(dev, "nand,cs", &cs); >> >> CS ids should be encoded in the reg property (see [1]). > > Is it your choice to only support a single CS or is it actually a > controller limitation?
Yes , its controller limitation to support only one CS
Regards Vadivel If the latter, it would be much better I think > to anticipate the addition of the support for another CS. And in > this case there are many places in this driver that should be > more generic. > >>> + if (ret) { >>> + dev_err(dev, "failed to get chip select: %d\n", ret); >>> + return ret; >>> + } >>> + >>> + ebu_host->cs = cs; >>> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cs0"); > > Thanks, > Miquèl >
| |