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    Subject[PATCH 4.19 008/131] arm64: Fake the IminLine size on systems affected by Neoverse-N1 #1542419
    Date
    From: James Morse <james.morse@arm.com>

    [ Upstream commit ee9d90be9ddace01b7fb126567e4b539fbe1f82f ]

    Systems affected by Neoverse-N1 #1542419 support DIC so do not need to
    perform icache maintenance once new instructions are cleaned to the PoU.
    For the errata workaround, the kernel hides DIC from user-space, so that
    the unnecessary cache maintenance can be trapped by firmware.

    To reduce the number of traps, produce a fake IminLine value based on
    PAGE_SIZE.

    Signed-off-by: James Morse <james.morse@arm.com>
    Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
    Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
    Signed-off-by: James Morse <james.morse@arm.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm64/include/asm/cache.h | 3 ++-
    arch/arm64/kernel/traps.c | 8 +++++++-
    2 files changed, 9 insertions(+), 2 deletions(-)

    diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
    index 5ee5bca8c24b1..baa684782358c 100644
    --- a/arch/arm64/include/asm/cache.h
    +++ b/arch/arm64/include/asm/cache.h
    @@ -22,6 +22,7 @@
    #define CTR_L1IP_MASK 3
    #define CTR_DMINLINE_SHIFT 16
    #define CTR_IMINLINE_SHIFT 0
    +#define CTR_IMINLINE_MASK 0xf
    #define CTR_ERG_SHIFT 20
    #define CTR_CWG_SHIFT 24
    #define CTR_CWG_MASK 15
    @@ -29,7 +30,7 @@
    #define CTR_DIC_SHIFT 29

    #define CTR_CACHE_MINLINE_MASK \
    - (0xf << CTR_DMINLINE_SHIFT | 0xf << CTR_IMINLINE_SHIFT)
    + (0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT)

    #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)

    diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
    index 253b7f84a5a0d..965595fe68045 100644
    --- a/arch/arm64/kernel/traps.c
    +++ b/arch/arm64/kernel/traps.c
    @@ -481,9 +481,15 @@ static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
    int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
    unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);

    - if (cpus_have_const_cap(ARM64_WORKAROUND_1542419))
    + if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) {
    + /* Hide DIC so that we can trap the unnecessary maintenance...*/
    val &= ~BIT(CTR_DIC_SHIFT);

    + /* ... and fake IminLine to reduce the number of traps. */
    + val &= ~CTR_IMINLINE_MASK;
    + val |= (PAGE_SHIFT - 2) & CTR_IMINLINE_MASK;
    + }
    +
    pt_regs_write_reg(regs, rt, val);

    arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
    --
    2.20.1


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